Signal vs Variable in VHDL: Key Differences and Usage Guide

Use signal in VHDL when you need to model hardware connections that update after a process ends, reflecting real hardware delays. Use variable inside processes for temporary storage that updates immediately within the same process execution.

Quick Comparison

Here is a quick table comparing signal and variable in VHDL based on key factors.

Factor	Signal	Variable
Scope	Visible outside processes	Local to process or subprogram
Update Timing	Updates after process completes (delta cycle)	Updates immediately within process
Hardware Modeling	Models physical wires/registers	Models temporary storage inside process
Usage	For communication between processes or with ports	For calculations and temporary values inside process
Default Value	Retains value until next assignment	Must be explicitly assigned before use
Synthesis Impact	Creates hardware registers or wires	No direct hardware unless assigned to signal

Key Differences

Signals represent hardware connections like wires or registers. When you assign a value to a signal inside a process, the new value does not take effect immediately but after the process finishes and a delta delay occurs. This models real hardware behavior where signals propagate with some delay.

Variables exist only inside processes or subprograms and update instantly when assigned. They are like temporary boxes used for calculations or intermediate results within the process execution. Variables do not represent physical hardware by themselves but help in writing clear and efficient code.

Because signals update after the process, multiple assignments to the same signal in one process overwrite each other, but only the last assignment is effective after the process ends. Variables update immediately, so multiple assignments in a process use the latest value right away. This difference is crucial when designing sequential logic or combinational logic in VHDL.

Code Comparison

This example shows how a signal updates in a clocked process to create a simple flip-flop behavior.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity signal_example is
  port(
    clk : in std_logic;
    d   : in std_logic;
    q   : out std_logic
  );
end entity;

architecture rtl of signal_example is
  signal q_reg : std_logic := '0';
begin
  process(clk)
  begin
    if rising_edge(clk) then
      q_reg <= d;  -- signal assignment
    end if;
  end process;

  q <= q_reg;
end architecture rtl;

Output

On each rising clock edge, output q updates to input d with one clock cycle delay.

Variable Equivalent

This example uses a variable inside a process to compute a value immediately before assigning it to a signal.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity variable_example is
  port(
    clk : in std_logic;
    d   : in std_logic;
    q   : out std_logic
  );
end entity;

architecture rtl of variable_example is
  signal q_reg : std_logic := '0';
begin
  process(clk)
    variable temp : std_logic;
  begin
    if rising_edge(clk) then
      temp := d;       -- variable assignment (immediate)
      q_reg <= temp;   -- signal assignment
    end if;
  end process;

  q <= q_reg;
end architecture rtl;

Output

On each rising clock edge, output q updates to input d with one clock cycle delay, using variable for intermediate step.

When to Use Which

Choose signal when: you need to model hardware connections, communicate between processes, or represent registers and wires that update with hardware timing.

Choose variable when: you want fast, immediate updates inside a process for calculations, temporary storage, or to simplify complex logic without creating hardware elements.

In short, use signal for hardware state and communication, and variable for internal process computations.

Key Takeaways

Use signal to model hardware connections that update after process execution.

Use variable for immediate updates and temporary storage inside processes.

Signals communicate between processes; variables do not.

Multiple assignments to a signal in one process only update after it finishes.

Variables help simplify logic without creating hardware elements.