VHDL Code for Encoder: Syntax, Example, and Tips

An encoder in VHDL converts active input lines into a binary code on the output. Use with-select or if-elsif statements inside a process to implement it. The code maps input signals to output bits representing the active input position.

Syntax

An encoder in VHDL typically uses a process block with if-elsif or with-select statements to check which input line is active and assign the corresponding binary code to the output.

Key parts:

• entity: Defines input and output ports.
• architecture: Contains the logic to convert inputs to output code.
• process: Monitors inputs and updates output.
• if-elsif or with-select: Selects which input is active.

vhdl

entity Encoder4to2 is
    Port (
        input : in std_logic_vector(3 downto 0);
        output : out std_logic_vector(1 downto 0)
    );
end Encoder4to2;

architecture Behavioral of Encoder4to2 is
begin
    process(input)
    begin
        if input(0) = '1' then
            output <= "00";
        elsif input(1) = '1' then
            output <= "01";
        elsif input(2) = '1' then
            output <= "10";
        elsif input(3) = '1' then
            output <= "11";
        else
            output <= "00"; -- default output
        end if;
    end process;
end Behavioral;

Example

This example shows a 4-to-2 encoder that converts one active input line among four into a 2-bit binary code output. It uses a process with if-elsif statements to detect the active input.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Encoder4to2 is
    Port (
        input : in std_logic_vector(3 downto 0);
        output : out std_logic_vector(1 downto 0)
    );
end Encoder4to2;

architecture Behavioral of Encoder4to2 is
begin
    process(input)
    begin
        if input(0) = '1' then
            output <= "00";
        elsif input(1) = '1' then
            output <= "01";
        elsif input(2) = '1' then
            output <= "10";
        elsif input(3) = '1' then
            output <= "11";
        else
            output <= "00"; -- default output when no input active
        end if;
    end process;
end Behavioral;

Common Pitfalls

Common mistakes when writing an encoder in VHDL include:

• Not handling the case when no inputs are active, which can cause undefined outputs.
• Multiple inputs active at the same time, which can cause ambiguous output.
• Forgetting to include all input lines in the if-elsif chain.
• Not using std_logic_vector or mixing signal types incorrectly.

Always ensure only one input is active or add priority logic to handle multiple active inputs.

vhdl

-- Wrong approach: No default case and no priority
process(input)
begin
    if input(0) = '1' then
        output <= "00";
    elsif input(1) = '1' then
        output <= "01";
    end if;
    -- Missing input(2) and input(3) cases and no else
end process;

-- Correct approach: Include all inputs and default
process(input)
begin
    if input(0) = '1' then
        output <= "00";
    elsif input(1) = '1' then
        output <= "01";
    elsif input(2) = '1' then
        output <= "10";
    elsif input(3) = '1' then
        output <= "11";
    else
        output <= "00"; -- default safe output
    end if;
end process;

Quick Reference

Tips for writing VHDL encoders:

• Use std_logic_vector for inputs and outputs.
• Use a process sensitive to inputs.
• Use if-elsif or with-select for priority encoding.
• Always include a default output for safety.
• Ensure only one input is active or define priority clearly.

Key Takeaways

Use a process with if-elsif statements to detect active input lines and assign binary output.

Always include a default output case to handle no active inputs safely.

Ensure only one input is active or implement priority logic to avoid ambiguous outputs.

Use std_logic_vector types for inputs and outputs for compatibility.

Test your encoder with all input combinations to verify correct output.