How to Use PLL in FPGA VHDL: Simple Guide and Example

To use a PLL in FPGA with VHDL, instantiate the vendor-specific PLL IP core in your design and connect its input clock and output clocks properly. Configure the PLL parameters using your FPGA tool to generate the desired clock frequencies, then use the PLL output clocks in your VHDL code as clock signals.

Syntax

A PLL in FPGA VHDL is usually instantiated as a component generated by the FPGA vendor's IP tool. The basic syntax includes declaring the PLL component, defining its ports (input clock, output clocks, reset, locked signal), and instantiating it in your architecture.

Key parts:

• Input Clock: The reference clock signal to the PLL.
• Output Clocks: One or more clocks generated at different frequencies or phases.
• Reset: Resets the PLL.
• Locked: Indicates when the PLL output clocks are stable.

vhdl

component PLL
  port(
    clk_in  : in  std_logic;
    reset   : in  std_logic;
    clk_out : out std_logic;
    locked  : out std_logic
  );
end component;

-- In architecture
pll_inst : PLL
  port map(
    clk_in  => clk_in_signal,
    reset   => reset_signal,
    clk_out => clk_out_signal,
    locked  => locked_signal
  );

Example

This example shows how to instantiate a PLL generated by a vendor tool (e.g., Intel/Altera or Xilinx) in VHDL. It assumes the PLL IP is configured to multiply the input clock by 2.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity pll_example is
  Port (
    clk_in  : in  std_logic;
    reset   : in  std_logic;
    clk_out : out std_logic;
    locked  : out std_logic
  );
end pll_example;

architecture Behavioral of pll_example is

  component pll_ip
    port(
      inclk0  : in  std_logic;
      areset  : in  std_logic;
      c0      : out std_logic;
      locked  : out std_logic
    );
  end component;

begin

  pll_inst : pll_ip
    port map(
      inclk0 => clk_in,
      areset => reset,
      c0     => clk_out,
      locked => locked
    );

end Behavioral;

Common Pitfalls

Common mistakes when using PLLs in FPGA VHDL include:

• Not using the vendor's IP generator to create the PLL component, which can cause incorrect parameters.
• Failing to connect the locked signal to ensure the output clock is stable before use.
• Ignoring the reset input, which can cause the PLL to not lock properly.
• Using the PLL output clock without proper synchronization in your design.

vhdl

---- Wrong: Using PLL output clock without checking locked signal
process(clk_out)
begin
  if rising_edge(clk_out) then
    -- logic here
  end if;
end process;

---- Right: Use locked signal to enable logic
process(clk_out)
begin
  if rising_edge(clk_out) and locked = '1' then
    -- logic here
  end if;
end process;

Quick Reference

Tips for using PLL in FPGA VHDL:

• Always generate PLL IP using your FPGA vendor's tool (Quartus for Intel, Vivado for Xilinx).
• Connect the locked output to control logic start.
• Use the PLL output clocks as your design clocks after lock.
• Reset the PLL properly during system reset.

Key Takeaways

Use the FPGA vendor's PLL IP core and instantiate it in your VHDL design.

Connect and monitor the PLL's locked signal to ensure stable output clocks.

Reset the PLL properly to allow it to lock correctly.

Use the PLL output clocks as your design clocks only after the PLL is locked.