VHDL Code for Binary to BCD Converter: Syntax and Example

A binary to BCD converter in VHDL converts a binary number into its decimal digits encoded in BCD format. This is typically done using a shift-and-add-3 algorithm inside a process block. The output is a set of 4-bit BCD digits representing the decimal equivalent of the binary input.

Syntax

The basic structure of a binary to BCD converter in VHDL includes an entity defining input and output ports, and an architecture implementing the conversion logic. The conversion often uses a process with a loop to shift bits and add 3 when needed.

• entity: Declares input binary and output BCD ports.
• architecture: Contains the conversion logic.
• process: Runs on input changes to perform conversion.
• shift-and-add-3: Algorithm to convert binary to BCD.

vhdl

entity BinaryToBCD is
    Port (
        binary_in : in  std_logic_vector(7 downto 0);
        bcd_out   : out std_logic_vector(11 downto 0)
    );
end BinaryToBCD;

architecture Behavioral of BinaryToBCD is
begin
    process(binary_in)
        variable shift_reg : std_logic_vector(19 downto 0);
        variable i : integer;
    begin
        shift_reg := (others => '0');
        shift_reg(7 downto 0) := binary_in;
        for i in 0 to 7 loop
            if unsigned(shift_reg(11 downto 8)) > 4 then
                shift_reg(11 downto 8) := std_logic_vector(unsigned(shift_reg(11 downto 8)) + 3);
            end if;
            if unsigned(shift_reg(15 downto 12)) > 4 then
                shift_reg(15 downto 12) := std_logic_vector(unsigned(shift_reg(15 downto 12)) + 3);
            end if;
            if unsigned(shift_reg(19 downto 16)) > 4 then
                shift_reg(19 downto 16) := std_logic_vector(unsigned(shift_reg(19 downto 16)) + 3);
            end if;
            shift_reg := shift_reg(18 downto 0) & '0';
        end loop;
        bcd_out <= shift_reg(19 downto 8);
    end process;
end Behavioral;

Example

This example converts an 8-bit binary number to a 3-digit BCD output. The input binary_in is an 8-bit vector, and the output bcd_out is a 12-bit vector representing three BCD digits.

The process uses the shift-and-add-3 method to convert binary to BCD by shifting bits and adding 3 to any BCD digit greater than 4.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity BinaryToBCD is
    Port (
        binary_in : in  std_logic_vector(7 downto 0);
        bcd_out   : out std_logic_vector(11 downto 0)
    );
end BinaryToBCD;

architecture Behavioral of BinaryToBCD is
begin
    process(binary_in)
        variable shift_reg : std_logic_vector(19 downto 0);
        variable i : integer;
    begin
        shift_reg := (others => '0');
        shift_reg(7 downto 0) := binary_in;
        for i in 0 to 7 loop
            if unsigned(shift_reg(11 downto 8)) > 4 then
                shift_reg(11 downto 8) := std_logic_vector(unsigned(shift_reg(11 downto 8)) + 3);
            end if;
            if unsigned(shift_reg(15 downto 12)) > 4 then
                shift_reg(15 downto 12) := std_logic_vector(unsigned(shift_reg(15 downto 12)) + 3);
            end if;
            if unsigned(shift_reg(19 downto 16)) > 4 then
                shift_reg(19 downto 16) := std_logic_vector(unsigned(shift_reg(19 downto 16)) + 3);
            end if;
            shift_reg := shift_reg(18 downto 0) & '0';
        end loop;
        bcd_out <= shift_reg(19 downto 8);
    end process;
end Behavioral;

Common Pitfalls

Common mistakes when writing a binary to BCD converter in VHDL include:

• Not initializing the shift register properly, causing incorrect output.
• Forgetting to add 3 when a BCD digit is greater than 4, which breaks the BCD conversion.
• Incorrect bit slicing or indexing in the shift register.
• Using signed arithmetic instead of unsigned for BCD digits.

Always use unsigned conversions for arithmetic and carefully check bit ranges.

vhdl

wrong approach:
process(binary_in)
    variable shift_reg : std_logic_vector(19 downto 0);
begin
    shift_reg := (others => '0');
    shift_reg(7 downto 0) := binary_in;
    -- Missing add 3 step
    for i in 0 to 7 loop
        shift_reg := shift_reg(18 downto 0) & '0';
    end loop;
    bcd_out <= shift_reg(19 downto 8);
end process;

correct approach:
process(binary_in)
    variable shift_reg : std_logic_vector(19 downto 0);
    variable i : integer;
begin
    shift_reg := (others => '0');
    shift_reg(7 downto 0) := binary_in;
    for i in 0 to 7 loop
        if unsigned(shift_reg(11 downto 8)) > 4 then
            shift_reg(11 downto 8) := std_logic_vector(unsigned(shift_reg(11 downto 8)) + 3);
        end if;
        if unsigned(shift_reg(15 downto 12)) > 4 then
            shift_reg(15 downto 12) := std_logic_vector(unsigned(shift_reg(15 downto 12)) + 3);
        end if;
        if unsigned(shift_reg(19 downto 16)) > 4 then
            shift_reg(19 downto 16) := std_logic_vector(unsigned(shift_reg(19 downto 16)) + 3);
        end if;
        shift_reg := shift_reg(18 downto 0) & '0';
    end loop;
    bcd_out <= shift_reg(19 downto 8);
end process;

Quick Reference

• Use a 20-bit shift register: lower 8 bits for binary input, upper 12 bits for BCD digits.
• Shift left one bit at a time, total shifts equal to binary input width.
• Add 3 to any BCD digit greater than 4 before shifting.
• Use unsigned type for arithmetic on BCD digits.
• Output the upper 12 bits as the BCD result.

Key Takeaways

Use the shift-and-add-3 algorithm to convert binary to BCD in VHDL.

Initialize a 20-bit shift register with the binary input in the lower bits.

Add 3 to any BCD digit greater than 4 before each shift to maintain valid BCD.

Perform shifts equal to the number of bits in the binary input.

Output the upper bits of the shift register as the BCD result.