VHDL Code for Round Robin Arbiter: Syntax and Example

A round robin arbiter in VHDL cycles through request signals fairly, granting access one at a time in a rotating order. The arbiter uses a pointer to track the last granted request and moves to the next request on each clock cycle. This ensures all requests get a chance without starvation.

Syntax

The round robin arbiter typically uses a process triggered by the clock and reset signals. It checks request inputs, grants access to one requester at a time, and updates a pointer to remember the last granted request.

Key parts include:

• clk: Clock signal to synchronize the arbiter.
• rst: Reset signal to initialize the arbiter state.
• request: Input vector of request signals.
• grant: Output vector indicating which request is granted.
• pointer: Internal signal to track the last granted request index.

vhdl

process(clk, rst)
begin
  if rst = '1' then
    grant <= (others => '0');
    pointer <= 0;
  elsif rising_edge(clk) then
    -- Check requests starting from pointer + 1
    -- Grant the first active request found
    -- Update pointer to granted request
  end if;
end process;

Example

This example shows a 4-request round robin arbiter. It grants one request at a time in a rotating order, ensuring fairness.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity round_robin_arbiter is
  port(
    clk     : in  std_logic;
    rst     : in  std_logic;
    request : in  std_logic_vector(3 downto 0);
    grant   : out std_logic_vector(3 downto 0)
  );
end entity;

architecture behavioral of round_robin_arbiter is
  signal pointer : integer range 0 to 3 := 0;
begin
  process(clk, rst)
    variable i : integer;
    variable idx : integer;
  begin
    if rst = '1' then
      grant <= (others => '0');
      pointer <= 0;
    elsif rising_edge(clk) then
      grant <= (others => '0');
      idx := (pointer + 1) mod 4;
      for i in 0 to 3 loop
        if request(idx) = '1' then
          grant(idx) <= '1';
          pointer <= idx;
          exit;
        end if;
        idx := (idx + 1) mod 4;
      end loop;
    end if;
  end process;
end behavioral;

Output

On each clock cycle, the arbiter grants one active request starting from the next index after the last granted, cycling through requests fairly.

Common Pitfalls

Common mistakes when writing a round robin arbiter in VHDL include:

• Not resetting the pointer on reset, causing unpredictable grants.
• Failing to wrap the pointer index correctly using modulo, which can cause index out of range errors.
• Granting multiple requests at once instead of only one.
• Not handling the case when no requests are active, which should result in no grants.

vhdl

process(clk, rst)
begin
  if rst = '1' then
    pointer <= 0;
    grant <= (others => '0');
  elsif rising_edge(clk) then
    -- Incorrect: grants multiple requests
    for i in 0 to 3 loop
      if request(i) = '1' then
        grant(i) <= '1'; -- grants all active requests
      else
        grant(i) <= '0';
      end if;
    end loop;
  end if;
end process;

-- Correct approach grants only one request as shown in the example section.

Quick Reference

Tips for implementing a round robin arbiter in VHDL:

• Use a pointer to track the last granted request index.
• Check requests starting from pointer + 1 and wrap around using modulo.
• Grant only the first active request found in the checking order.
• Reset pointer and grants on reset signal.
• Use a synchronous process triggered by clock and reset.

Key Takeaways

A round robin arbiter cycles through requests fairly using a pointer and modulo arithmetic.

Only one request should be granted per clock cycle to avoid conflicts.

Always reset the pointer and grant signals to a known state on reset.

Check requests starting from the next index after the last granted to ensure fairness.

Handle the case when no requests are active by granting none.