VHDL Code for 2-to-1 Multiplexer: Syntax and Example

A 2-to-1 multiplexer in VHDL selects one of two inputs based on a single select signal. You can write it using a simple process block or with concurrent when-else statements to assign the output based on the select input.

Syntax

The basic syntax for a 2-to-1 multiplexer in VHDL involves defining an entity with two data inputs, one select input, and one output. The architecture describes how the output depends on the select signal.

• entity: Declares inputs and outputs.
• architecture: Contains the logic to select between inputs.
• process or when-else: Used to implement the selection.

vhdl

entity mux2to1 is
    Port (
        a : in std_logic;
        b : in std_logic;
        sel : in std_logic;
        y : out std_logic
    );
end mux2to1;

architecture Behavioral of mux2to1 is
begin
    y <= a when sel = '0' else b;
end Behavioral;

Example

This example shows a complete 2-to-1 multiplexer using a when-else statement. The output y is a when sel is '0', otherwise it is b. This code can be simulated or synthesized for hardware.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2to1 is
    Port (
        a : in std_logic;
        b : in std_logic;
        sel : in std_logic;
        y : out std_logic
    );
end mux2to1;

architecture Behavioral of mux2to1 is
begin
    y <= a when sel = '0' else b;
end Behavioral;

Common Pitfalls

Common mistakes when writing a 2-to-1 multiplexer in VHDL include:

• Forgetting to include all inputs and outputs in the entity.
• Using incorrect signal types (use std_logic for single-bit signals).
• Not handling all select signal values, especially if using if-else inside a process.
• Mixing concurrent and sequential assignments incorrectly.

Here is a wrong and right way example:

vhdl

architecture Wrong of mux2to1 is
begin
    process(a, b, sel)
    begin
        if sel = '0' then
            y <= a;
        end if; -- Missing else branch causes latch
    end process;
end Wrong;

architecture Right of mux2to1 is
begin
    process(a, b, sel)
    begin
        if sel = '0' then
            y <= a;
        else
            y <= b;
        end if;
    end process;
end Right;

Quick Reference

Component	Description	Example
entity	Defines inputs and outputs	entity mux2to1 is Port (a, b, sel: in std_logic; y: out std_logic); end mux2to1;
architecture	Describes behavior or structure	architecture Behavioral of mux2to1 is begin y <= a when sel = '0' else b; end Behavioral;
when-else	Concurrent conditional assignment	y <= a when sel = '0' else b;
process	Sequential logic block	process(a,b,sel) begin if sel='0' then y<=a; else y<=b; end if; end process;

Key Takeaways

Use a simple when-else statement for clean 2-to-1 multiplexer code in VHDL.

Always define all inputs and outputs clearly in the entity block.

Ensure all select signal cases are handled to avoid unintended latches.

Use std_logic type for single-bit signals in VHDL.

Test your multiplexer with simulation to verify correct selection behavior.