How to Use Generate Statement in VHDL: Syntax and Examples

In VHDL, the generate statement is used to create repetitive or conditional hardware structures by replicating code blocks. It works with a for or if clause inside an architecture to generate multiple instances or conditional logic.

Syntax

The generate statement has two main forms: for-generate and if-generate. The for-generate repeats a block of code for a range of values, while the if-generate conditionally includes code based on a boolean expression.

• for-generate: repeats code for each value in a range.
• if-generate: includes code only if a condition is true.

vhdl

label: for i in 0 to N generate
    -- statements using i
end generate label;

label: if condition generate
    -- statements executed if condition is true
end generate label;

Example

This example shows how to use a for-generate statement to create 4 identical AND gates connecting bits of two 4-bit vectors.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndArray is
    Port (
        A : in STD_LOGIC_VECTOR(3 downto 0);
        B : in STD_LOGIC_VECTOR(3 downto 0);
        Y : out STD_LOGIC_VECTOR(3 downto 0)
    );
end AndArray;

architecture Behavioral of AndArray is
begin
    gen_and: for i in 0 to 3 generate
    begin
        Y(i) <= A(i) and B(i);
    end generate gen_and;
end Behavioral;

Common Pitfalls

Common mistakes when using generate statements include:

• Forgetting to label the generate block, which is required.
• Using signals or variables incorrectly inside the generate block.
• Misusing the range in for-generate causing out-of-bound errors.
• Trying to use generate outside an architecture body.

Always ensure the generate block is properly labeled and placed inside an architecture.

vhdl

wrong_generate: for i in 0 to 4 generate  -- Error: index 4 out of range if vectors are 3 downto 0
begin
    Y(i) <= A(i) and B(i);
end generate wrong_generate;

correct_generate: for i in 0 to 3 generate
begin
    Y(i) <= A(i) and B(i);
end generate correct_generate;

Quick Reference

Generate Statement Type	Purpose	Syntax Example
for-generate	Repeat code for a range of values	label: for i in 0 to N generate ... end generate label;
if-generate	Conditionally include code	label: if condition generate ... end generate label;

Key Takeaways

Use generate inside architectures to create repetitive or conditional hardware blocks.

Always label your generate blocks to avoid syntax errors.

Use for-generate for loops and if-generate for conditional code inclusion.

Check index ranges carefully to prevent out-of-bound errors.

Generate statements help write cleaner, scalable VHDL code for repeated structures.