VHDL Code for Full Adder: Syntax and Example

A full adder in VHDL can be created using an entity to define inputs and outputs, and an architecture to describe the logic using signal assignments. The full adder adds three bits (two inputs and a carry-in) and produces a sum and carry-out.

Syntax

The full adder in VHDL uses an entity to declare inputs and outputs: A, B, and Cin as inputs, and Sum and Cout as outputs. The architecture block contains the logic using Boolean expressions for sum and carry.

• entity: Defines the interface.
• architecture: Contains the logic implementation.
• signal assignments: Describe how outputs depend on inputs.

vhdl

entity FullAdder is
    Port (
        A    : in  std_logic;
        B    : in  std_logic;
        Cin  : in  std_logic;
        Sum  : out std_logic;
        Cout : out std_logic
    );
end FullAdder;

architecture Behavioral of FullAdder is
begin
    Sum  <= A xor B xor Cin;
    Cout <= (A and B) or (B and Cin) or (Cin and A);
end Behavioral;

Example

This example shows a complete VHDL code for a full adder. It demonstrates how to add two bits and a carry-in to produce a sum and carry-out.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FullAdder is
    Port (
        A    : in  std_logic;
        B    : in  std_logic;
        Cin  : in  std_logic;
        Sum  : out std_logic;
        Cout : out std_logic
    );
end FullAdder;

architecture Behavioral of FullAdder is
begin
    Sum  <= A xor B xor Cin;
    Cout <= (A and B) or (B and Cin) or (Cin and A);
end Behavioral;

Output

When simulated, the full adder outputs Sum and Cout according to the truth table of a full adder, e.g., A=1, B=1, Cin=0 results in Sum=0 and Cout=1.

Common Pitfalls

Common mistakes include:

• Using incorrect logic operators (e.g., using and as a function instead of the operator in VHDL syntax).
• Forgetting to include the library IEEE; and use IEEE.STD_LOGIC_1164.ALL; statements.
• Mixing signal and variable assignments incorrectly.
• Not matching port names between entity and architecture.

Always ensure the logic expressions correctly represent the full adder truth table.

vhdl

entity FullAdderWrong is
    Port (
        A    : in  std_logic;
        B    : in  std_logic;
        Cin  : in  std_logic;
        Sum  : out std_logic;
        Cout : out std_logic
    );
end FullAdderWrong;

architecture Behavioral of FullAdderWrong is
begin
    -- Wrong: Using 'and' as a function instead of operator
    Sum  <= A xor B xor Cin;
    Cout <= and(A, B) or and(B, Cin) or and(Cin, A); -- Incorrect
end Behavioral;

-- Correct version:
architecture BehavioralCorrect of FullAdderWrong is
begin
    Sum  <= A xor B xor Cin;
    Cout <= (A and B) or (B and Cin) or (Cin and A);
end BehavioralCorrect;

Quick Reference

Remember these key points for a VHDL full adder:

• Inputs: A, B, Cin (all std_logic)
• Outputs: Sum, Cout (std_logic)
• Sum logic: Sum <= A xor B xor Cin;
• Carry logic: Cout <= (A and B) or (B and Cin) or (Cin and A);
• Include IEEE library and std_logic package.

Key Takeaways

Define inputs and outputs clearly in the entity block using std_logic type.

Use xor for sum and a combination of and/or for carry logic in the architecture.

Always include IEEE library and std_logic package for proper signal types.

Check logic expressions carefully to match the full adder truth table.

Avoid syntax errors by using correct VHDL operators and matching port names.