VHDL Code for Booth Multiplier: Syntax and Example

A Booth multiplier in VHDL uses a process to implement Booth's algorithm for signed multiplication by encoding the multiplier bits. The code typically includes registers for multiplicand, multiplier, and accumulator, and a control process to perform shifts and adds based on Booth encoding.

Syntax

The Booth multiplier in VHDL usually consists of these parts:

• Entity declaration: Defines inputs (multiplicand, multiplier) and output (product).
• Architecture: Contains signals for registers and the main process implementing Booth's algorithm.
• Process block: Runs on clock and reset, performs shifts, adds, and controls the multiplication steps.

vhdl

entity BoothMultiplier is
    Port (
        clk       : in  std_logic;
        reset     : in  std_logic;
        start     : in  std_logic;
        multiplicand : in  signed(7 downto 0);
        multiplier   : in  signed(7 downto 0);
        product      : out signed(15 downto 0);
        ready        : out std_logic
    );
end BoothMultiplier;

Example

This example shows a complete 8-bit Booth multiplier in VHDL. It multiplies two signed 8-bit numbers and outputs a 16-bit signed product. The start signal begins the multiplication, and ready signals when the result is valid.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity BoothMultiplier is
    Port (
        clk       : in  std_logic;
        reset     : in  std_logic;
        start     : in  std_logic;
        multiplicand : in  signed(7 downto 0);
        multiplier   : in  signed(7 downto 0);
        product      : out signed(15 downto 0);
        ready        : out std_logic
    );
end BoothMultiplier;

architecture Behavioral of BoothMultiplier is
    signal A       : signed(15 downto 0) := (others => '0');
    signal Q       : signed(7 downto 0) := (others => '0');
    signal Q_1     : std_logic := '0';
    signal M       : signed(15 downto 0) := (others => '0');
    signal count   : integer range 0 to 8 := 0;
    signal busy    : std_logic := '0';
begin
    process(clk, reset)
    begin
        if reset = '1' then
            A <= (others => '0');
            Q <= (others => '0');
            Q_1 <= '0';
            M <= (others => '0');
            count <= 0;
            busy <= '0';
            product <= (others => '0');
            ready <= '0';
        elsif rising_edge(clk) then
            if start = '1' and busy = '0' then
                -- Load inputs
                M <= resize(multiplicand, 16);
                Q <= multiplier;
                A <= (others => '0');
                Q_1 <= '0';
                count <= 8;
                busy <= '1';
                ready <= '0';
            elsif busy = '1' then
                -- Booth encoding step
                case Q(0) & Q_1 is
                    when "10" =>
                        A <= A - M;
                    when "01" =>
                        A <= A + M;
                    when others =>
                        null;
                end case;

                -- Arithmetic right shift of A, Q, Q_1
                variable combined : signed(16 downto 0);
                combined := A & Q(0);
                combined := combined sra 1;
                A <= combined(16 downto 1);
                Q <= combined(0) & Q(7 downto 1);
                Q_1 <= Q(0);

                count <= count - 1;

                if count = 0 then
                    busy <= '0';
                    product <= A & Q;
                    ready <= '1';
                end if;
            end if;
        end if;
    end process;
end Behavioral;

Output

When simulated, after asserting start, the product output holds the signed multiplication result of multiplicand and multiplier after 8 clock cycles, and ready goes high.

Common Pitfalls

Common mistakes when coding a Booth multiplier in VHDL include:

• Not resizing signals properly, causing overflow or incorrect results.
• Incorrect handling of the arithmetic right shift, which must preserve the sign bit.
• Forgetting to initialize or reset internal registers and control signals.
• Mixing up the order of bits during shifts and updates of Q_1.
• Not controlling the start and ready signals properly, leading to race conditions.

vhdl

wrong: A <= A srl 1; -- Logical shift right (wrong for signed)
right: A <= A sra 1; -- Arithmetic shift right (correct for signed)

Quick Reference

Tips for implementing Booth multiplier in VHDL:

• Use signed type from ieee.numeric_std for arithmetic operations.
• Always perform arithmetic right shifts (sra) to keep sign bits.
• Initialize all signals on reset to avoid unknown states.
• Use a counter to track the number of bits processed (usually equal to multiplier width).
• Control start and ready signals to manage operation flow.

Key Takeaways

Booth multiplier in VHDL uses registers and a process to implement signed multiplication with shifts and adds.

Use arithmetic right shifts (sra) to preserve sign bits during shifting.

Initialize and reset all internal signals to avoid incorrect results.

Control start and ready signals to manage multiplication timing.

Resize inputs and outputs properly to handle signed arithmetic without overflow.