How to Instantiate Component in VHDL: Syntax and Example

In VHDL, you instantiate a component by declaring it in the architecture and then using the component keyword followed by a port map to connect signals. This creates an instance of the component inside your design, allowing reuse of code modules.

Syntax

To instantiate a component in VHDL, first declare the component interface inside the architecture or a package. Then create an instance using the component name and connect its ports with signals using port map.

• component: declares the interface of the component.
• instance_name: a unique name for this instance.
• port map: connects component ports to signals in your design.

vhdl

architecture Behavioral of TopModule is
  component MyComponent
    port(
      input1 : in std_logic;
      output1 : out std_logic
    );
  end component;

  signal sig_in : std_logic := '0';
  signal sig_out : std_logic;
begin
  U1: MyComponent port map(
    input1 => sig_in,
    output1 => sig_out
  );
end Behavioral;

Example

This example shows how to instantiate a simple component that inverts a signal. The top module declares the component, defines signals, and connects them to the component instance.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Inverter is
  port(
    A : in std_logic;
    Y : out std_logic
  );
end Inverter;

architecture Behavioral of Inverter is
begin
  Y <= not A;
end Behavioral;

entity TopModule is
  port(
    input_signal : in std_logic;
    output_signal : out std_logic
  );
end TopModule;

architecture Behavioral of TopModule is
  component Inverter
    port(
      A : in std_logic;
      Y : out std_logic
    );
  end component;

  signal internal_in : std_logic;
  signal internal_out : std_logic;
begin
  internal_in <= input_signal;

  U1: Inverter port map(
    A => internal_in,
    Y => internal_out
  );

  output_signal <= internal_out;
end Behavioral;

Common Pitfalls

Common mistakes when instantiating components include:

• Not declaring the component before instantiation.
• Mismatching port names or types between the component and the instance.
• Forgetting to connect all ports in the port map.
• Using the same instance name multiple times.

Always check that the component declaration matches the actual entity and that signals connected have compatible types.

vhdl

architecture Behavioral of TopModule is
  -- Wrong: Missing component declaration
  signal sig_in : std_logic;
  signal sig_out : std_logic;
begin
  -- This will cause an error because MyComponent is not declared
  U1: MyComponent port map(
    input1 => sig_in,
    output1 => sig_out
  );
end Behavioral;

-- Correct way:
architecture Behavioral of TopModule is
  component MyComponent
    port(
      input1 : in std_logic;
      output1 : out std_logic
    );
  end component;

  signal sig_in : std_logic;
  signal sig_out : std_logic;
begin
  U1: MyComponent port map(
    input1 => sig_in,
    output1 => sig_out
  );
end Behavioral;

Quick Reference

Remember these key points when instantiating components in VHDL:

• Declare the component interface before instantiation.
• Use a unique instance name for each component.
• Connect ports using port map with matching signal types.
• Check that all ports are connected to avoid synthesis errors.

Key Takeaways

Always declare the component interface before instantiating it in your architecture.

Use port map to connect component ports to signals in your design.

Ensure port names and signal types match exactly to avoid errors.

Give each component instance a unique name to prevent conflicts.

Connect all ports to signals to ensure proper functionality.