How to Use If Else in VHDL Process: Syntax and Example

In VHDL, use if else statements inside a process block to make decisions based on signals or variables. The if condition is checked first, and if false, the else part runs. This helps control signal assignments depending on conditions.

Syntax

The if else statement inside a VHDL process lets you choose between actions based on conditions.

• if condition then: Checks if the condition is true.
• elsif condition then: (optional) Checks another condition if the first is false.
• else: Runs if all previous conditions are false.
• end if;: Ends the if statement.

This structure must be inside a process block.

vhdl

process(signal_name)
begin
    if condition then
        -- statements when condition is true
    elsif another_condition then
        -- statements when another_condition is true
    else
        -- statements when all conditions are false
    end if;
end process;

Example

This example shows a simple process that sets an output signal y to '1' if input a is '1', sets y to '0' if input b is '1', and otherwise sets y to 'Z' (high impedance).

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity IfElseExample is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           y : out STD_LOGIC);
end IfElseExample;

architecture Behavioral of IfElseExample is
begin
    process(a, b)
    begin
        if a = '1' then
            y <= '1';
        elsif b = '1' then
            y <= '0';
        else
            y <= 'Z';
        end if;
    end process;
end Behavioral;

Output

When a='1', y='1'; when a='0' and b='1', y='0'; otherwise y='Z'.

Common Pitfalls

Common mistakes when using if else in VHDL processes include:

• Forgetting to include end if; to close the if statement.
• Not listing all signals in the process sensitivity list, causing simulation mismatches.
• Using if statements outside a process or concurrent block incorrectly.
• Assigning signals improperly inside the process (use <= for signals, not =).

vhdl

process(a, b)
begin
    if a = '1' then
        y = '1'; -- WRONG: should use '<=' for signals
    end if;
end process;

-- Correct version:
process(a, b)
begin
    if a = '1' then
        y <= '1';
    end if;
end process;

Quick Reference

Keyword	Description
if	Starts the condition check
elsif	Checks another condition if previous is false
else	Runs if all previous conditions are false
end if;	Ends the if statement
process	Block where if else statements are used
<=	Signal assignment inside process

Key Takeaways

Use if else statements inside a process block to control signal assignments based on conditions.

Always close if statements with end if; and include all relevant signals in the process sensitivity list.

Use <= for signal assignments inside processes, not =.

Include elsif for multiple conditions and else for default actions.

If conditions are not met, else block ensures a defined output.