How to Use Component in VHDL: Syntax and Example

In VHDL, you use a component to declare a reusable hardware block and then instantiate it inside an architecture using the component instantiation syntax. This involves declaring the component interface, then creating an instance that connects signals to the component ports.

Syntax

To use a component in VHDL, first declare the component with its ports inside the architecture or a package. Then instantiate it by giving it a label, specifying the component name, and mapping its ports to signals.

• component declaration: defines the interface (ports) of the component.
• instantiation: creates an instance of the component and connects signals.
• port map: links the component ports to signals in the design.

vhdl

architecture Behavioral of TopModule is
  component MyComponent
    port(
      a : in std_logic;
      b : out std_logic
    );
  end component;

  signal sig_a : std_logic;
  signal sig_b : std_logic;
begin
  U1: MyComponent port map(
    a => sig_a,
    b => sig_b
  );
end Behavioral;

Example

This example shows how to declare a simple component that inverts a signal and instantiate it inside a top-level module.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Inverter is
  port(
    input_sig : in std_logic;
    output_sig : out std_logic
  );
end Inverter;

architecture Behavioral of Inverter is
begin
  output_sig <= not input_sig;
end Behavioral;

entity TopModule is
  port(
    in_sig : in std_logic;
    out_sig : out std_logic
  );
end TopModule;

architecture Behavioral of TopModule is
  component Inverter
    port(
      input_sig : in std_logic;
      output_sig : out std_logic
    );
  end component;

  signal internal_sig : std_logic;
begin
  U1: Inverter port map(
    input_sig => in_sig,
    output_sig => internal_sig
  );

  out_sig <= internal_sig;
end Behavioral;

Common Pitfalls

Common mistakes when using components in VHDL include:

• Forgetting to declare the component before instantiation.
• Mismatching port names or types between the component declaration and the actual entity.
• Not connecting all ports in the port map, which can cause synthesis errors.
• Using signals instead of ports or vice versa incorrectly.

Always ensure the component declaration matches the entity interface exactly and all ports are connected.

vhdl

architecture Behavioral of TopModule is
  -- Wrong: Missing component declaration
  signal sig_a : std_logic;
  signal sig_b : std_logic;
begin
  -- This will cause an error because MyComponent is not declared
  U1: MyComponent port map(
    a => sig_a,
    b => sig_b
  );
end Behavioral;

-- Correct way includes component declaration as shown in the Syntax section.

Quick Reference

Component Usage Tips:

• Declare the component interface before instantiation.
• Use clear and consistent port names.
• Map all ports explicitly in port map.
• Use signals to connect component ports inside architecture.
• Consider using packages to share component declarations across files.

Key Takeaways

Always declare the component interface before instantiating it in your architecture.

Use port map to connect component ports to signals in your design.

Ensure port names and types match exactly between component declaration and entity.

Connect all ports explicitly to avoid synthesis errors.

Consider using packages to reuse component declarations across multiple designs.