VHDL Code for Memory Controller: Syntax and Example

A memory controller in VHDL manages read and write operations to memory using signals like address, data_in, data_out, read_enable, and write_enable. It controls when data is stored or retrieved by checking these signals and updating memory accordingly.

Syntax

A basic memory controller in VHDL uses a process block triggered by a clock and reset. It checks read_enable and write_enable signals to decide whether to read from or write to memory at the given address. The data_in is written to memory on write, and data_out outputs the stored data on read.

• clk: Clock signal to synchronize operations.
• reset: Resets memory or controller state.
• address: Memory location to access.
• data_in: Data to write into memory.
• data_out: Data read from memory.
• read_enable: Signal to enable reading.
• write_enable: Signal to enable writing.

vhdl

process(clk, reset)
begin
  if reset = '1' then
    -- reset logic here
  elsif rising_edge(clk) then
    if write_enable = '1' then
      memory(to_integer(unsigned(address))) <= data_in;
    elsif read_enable = '1' then
      data_out <= memory(to_integer(unsigned(address)));
    end if;
  end if;
end process;

Example

This example shows a simple synchronous memory controller for a 16-word memory with 8-bit data width. It supports reading and writing data based on control signals.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity MemoryController is
  port(
    clk         : in std_logic;
    reset       : in std_logic;
    address     : in std_logic_vector(3 downto 0); -- 16 locations
    data_in     : in std_logic_vector(7 downto 0);
    data_out    : out std_logic_vector(7 downto 0);
    read_enable : in std_logic;
    write_enable: in std_logic
  );
end MemoryController;

architecture Behavioral of MemoryController is
  type memory_array is array (0 to 15) of std_logic_vector(7 downto 0);
  signal memory : memory_array := (others => (others => '0'));
begin
  process(clk, reset)
  begin
    if reset = '1' then
      memory <= (others => (others => '0'));
      data_out <= (others => '0');
    elsif rising_edge(clk) then
      if write_enable = '1' then
        memory(to_integer(unsigned(address))) <= data_in;
      elsif read_enable = '1' then
        data_out <= memory(to_integer(unsigned(address)));
      end if;
    end if;
  end process;
end Behavioral;

Output

No direct console output; the memory controller updates internal memory and outputs data_out based on inputs.

Common Pitfalls

Common mistakes when writing a VHDL memory controller include:

• Not synchronizing read/write operations with the clock, causing timing issues.
• Forgetting to reset memory or output signals, leading to undefined states.
• Using combinational reads without clock, which can cause glitches.
• Incorrectly converting address from std_logic_vector to integer.

Always use rising_edge(clk) and proper type conversions.

vhdl

process(clk)
begin
  if clk = '1' then  -- Incorrect: level sensitive, not edge sensitive
    if write_enable = '1' then
      memory(to_integer(unsigned(address))) <= data_in;
    end if;
  end if;
end process;

-- Correct way:
process(clk)
begin
  if rising_edge(clk) then
    if write_enable = '1' then
      memory(to_integer(unsigned(address))) <= data_in;
    end if;
  end if;
end process;

Quick Reference

Tips for writing a VHDL memory controller:

• Use synchronous processes triggered by rising_edge(clk).
• Reset memory and outputs to known states.
• Convert addresses properly using to_integer(unsigned(address)).
• Separate read and write enables to avoid conflicts.
• Test with simple testbenches to verify behavior.

Key Takeaways

Always synchronize memory read/write operations with the clock using rising_edge(clk).

Reset memory and output signals to avoid undefined states.

Use proper type conversion for address signals from std_logic_vector to integer.

Separate read and write enable signals to prevent simultaneous conflicting operations.

Test your memory controller with simple testbenches to ensure correct behavior.