VHDL Code for ALU: Syntax, Example, and Common Pitfalls

An ALU in VHDL is created using an entity to define inputs and outputs and an architecture to describe operations like addition, subtraction, and logic. You use a case statement inside a process to select the operation based on an opcode input.

Syntax

The ALU in VHDL is defined by an entity that declares inputs (operands and operation code) and outputs (result and flags). The architecture contains a process block where the operation is selected using a case statement based on the opcode.

• entity: Defines the ALU interface.
• architecture: Contains the logic for operations.
• process: Runs when inputs change to compute the output.
• case: Chooses the operation based on opcode.

vhdl

entity ALU is
    Port (
        A       : in  std_logic_vector(3 downto 0);
        B       : in  std_logic_vector(3 downto 0);
        OpCode  : in  std_logic_vector(2 downto 0);
        Result  : out std_logic_vector(3 downto 0);
        Zero    : out std_logic
    );
end ALU;

architecture Behavioral of ALU is
begin
    process(A, B, OpCode)
    begin
        case OpCode is
            when "000" => Result <= std_logic_vector(unsigned(A) + unsigned(B));          -- Addition
            when "001" => Result <= std_logic_vector(unsigned(A) - unsigned(B));          -- Subtraction
            when "010" => Result <= A and B;        -- AND
            when "011" => Result <= A or B;         -- OR
            when "100" => Result <= not A;          -- NOT
            when others => Result <= (others => '0'); -- Default
        end case;
        Zero <= '1' when Result = "0000" else '0';
    end process;
end Behavioral;

Example

This example shows a simple 4-bit ALU that performs addition, subtraction, AND, OR, and NOT operations based on a 3-bit opcode input. It also sets a zero flag when the result is zero.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Port (
        A       : in  std_logic_vector(3 downto 0);
        B       : in  std_logic_vector(3 downto 0);
        OpCode  : in  std_logic_vector(2 downto 0);
        Result  : out std_logic_vector(3 downto 0);
        Zero    : out std_logic
    );
end ALU;

architecture Behavioral of ALU is
begin
    process(A, B, OpCode)
    begin
        case OpCode is
            when "000" => Result <= std_logic_vector(unsigned(A) + unsigned(B));
            when "001" => Result <= std_logic_vector(unsigned(A) - unsigned(B));
            when "010" => Result <= A and B;
            when "011" => Result <= A or B;
            when "100" => Result <= not A;
            when others => Result <= (others => '0');
        end case;
        Zero <= '1' when Result = "0000" else '0';
    end process;
end Behavioral;

Common Pitfalls

Common mistakes when writing a VHDL ALU include:

• Not converting std_logic_vector to unsigned or signed before arithmetic operations, causing errors or unexpected results.
• Forgetting to handle the others case in the case statement, which can lead to latches or undefined outputs.
• Not updating the zero flag correctly after operations.

Always use proper type conversions and cover all cases in your case statements.

vhdl

wrong:
Result <= A + B;  -- This causes a type mismatch error

right:
Result <= std_logic_vector(unsigned(A) + unsigned(B));

Quick Reference

Component	Description
entity	Defines ALU inputs and outputs
architecture	Contains the logic for ALU operations
process	Executes when inputs change to compute output
case statement	Selects operation based on opcode
std_logic_vector	Used for input/output bit vectors
unsigned()	Converts std_logic_vector for arithmetic

Key Takeaways

Use an entity to define ALU inputs and outputs clearly.

Perform arithmetic by converting std_logic_vector to unsigned.

Use a case statement inside a process to select ALU operations.

Always handle the 'others' case to avoid unintended latches.

Set flags like zero correctly after each operation.