How Event Driven Simulation Works in VHDL Explained

In VHDL, event driven simulation means the simulator updates signals and runs processes only when signal changes (events) happen. This approach efficiently models hardware by reacting to changes instead of running all code continuously.

Syntax

VHDL uses process blocks sensitive to signals. The sensitivity list defines which signals trigger the process when they change (events). Inside the process, signal assignments update outputs based on inputs.

Key parts:

• process (signal_list): Runs when any signal in the list changes.
• if rising_edge(clock): Common way to trigger on clock signal edges.
• signal <= value;: Assigns new value to a signal, causing an event.

vhdl

process (clk, reset)
begin
  if reset = '1' then
    output <= '0';
  elsif rising_edge(clk) then
    output <= input_signal;
  end if;
end process;

Example

This example shows a simple flip-flop that updates output on the rising edge of a clock signal. The process runs only when clk or reset changes, demonstrating event driven simulation.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity flip_flop is
  port (
    clk : in std_logic;
    reset : in std_logic;
    d : in std_logic;
    q : out std_logic
  );
end flip_flop;

architecture behavior of flip_flop is
begin
  process(clk, reset)
  begin
    if reset = '1' then
      q <= '0';
    elsif rising_edge(clk) then
      q <= d;
    end if;
  end process;
end behavior;

Output

When reset='1', output q is '0'. On each rising edge of clk, q updates to d's value.

Common Pitfalls

Common mistakes include:

• Not listing all signals that should trigger the process in the sensitivity list, causing simulation mismatches.
• Using variables instead of signals inside processes, which do not cause events.
• Forgetting to use rising_edge(clock) for clocked processes, leading to incorrect timing.

vhdl

process(clk)
begin
  -- Wrong: missing reset in sensitivity list
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

-- Correct:
process(clk, reset)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Quick Reference

Concept	Description
Event	A change in a signal value that triggers processes.
Sensitivity List	Signals that cause the process to run when they change.
Process	Block of code that runs when an event occurs on signals in sensitivity list.
rising_edge(signal)	Function to detect a rising clock edge event.
Signal Assignment	Updates signal value and creates an event.

Key Takeaways

VHDL simulation runs processes only when signals in their sensitivity list change, making it event driven.

Use sensitivity lists correctly to ensure processes trigger on all relevant signal changes.

Clocked processes commonly use rising_edge() to detect clock events.

Signal assignments inside processes cause events that update outputs.

Missing signals in sensitivity lists or incorrect edge detection cause simulation errors.