How to Create Custom Type in Package in VHDL

In VHDL, you create a custom type inside a package by declaring it within the package's declaration section. This allows you to reuse the type across multiple design units by including the package with use statements.

Syntax

To create a custom type in a VHDL package, declare the type inside the package declaration block. Then, define the package body if needed. Use the package in your design units to access the type.

• package: Defines the container for types and declarations.
• type: Declares the new custom type.
• use: Imports the package to use the custom type.

vhdl

package MyTypes is
    type StateType is (IDLE, RUNNING, STOPPED);
end package MyTypes;

package body MyTypes is
    -- Optional: implementation details
end package body MyTypes;

Example

This example shows how to define a custom enumeration type StateType inside a package and then use it in an entity and architecture.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use work.MyTypes.all;

package MyTypes is
    type StateType is (IDLE, RUNNING, STOPPED);
end package MyTypes;

package body MyTypes is
end package body MyTypes;

entity Machine is
    port(
        clk : in std_logic;
        reset : in std_logic;
        state_out : out StateType
    );
end entity Machine;

architecture Behavioral of Machine is
    signal current_state : StateType := IDLE;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            current_state <= IDLE;
        elsif rising_edge(clk) then
            case current_state is
                when IDLE => current_state <= RUNNING;
                when RUNNING => current_state <= STOPPED;
                when STOPPED => current_state <= IDLE;
            end case;
        end if;
    end process;
    state_out <= current_state;
end architecture Behavioral;

Output

No direct console output; the signal 'state_out' cycles through IDLE, RUNNING, STOPPED states on clock edges.

Common Pitfalls

Common mistakes when creating custom types in packages include:

• Forgetting to include the package with use work.PackageName.all; in the design units.
• Declaring the type outside the package declaration block.
• Not compiling the package before using it in other files.
• Using the package body unnecessarily when only type declarations are needed.

vhdl

package WrongPackage is
    -- Incorrect: type declared outside package declaration
end package WrongPackage;

-- Correct way:
package CorrectPackage is
    type MyType is (A, B, C);
end package CorrectPackage;

Quick Reference

Concept	Description
package	Container for types and declarations reusable across designs
type	Defines a new custom data type (e.g., enumeration, record)
use	Imports package contents into design units
package body	Optional implementation part of package, usually empty for types
compilation order	Compile package before using it in other files

Key Takeaways

Declare custom types inside a package declaration for reuse.

Always compile the package before using its types in other units.

Use the 'use work.PackageName.all;' statement to access package types.

Keep type declarations in the package declaration, not the body.

Packages help organize and share types across multiple VHDL files.