How to Model ROM in VHDL: Syntax and Example

To model ROM in VHDL, define a constant array with fixed data and use a process or with-select statement to output data based on the address input. This creates a read-only memory where data cannot be changed during simulation or synthesis.

Syntax

Modeling ROM in VHDL typically involves defining a constant array to hold the fixed data values and using a process or with-select statement to select the output based on the address input.

The main parts are:

• type: Defines the data type of ROM contents.
• constant: Holds the ROM data values.
• address input: Selects which data to output.
• output: The data read from ROM.

vhdl

type rom_type is array (0 to 3) of std_logic_vector(7 downto 0);
constant ROM : rom_type := (
  0 => "00000001",
  1 => "00000010",
  2 => "00000100",
  3 => "00001000"
);

process(address)
begin
  data_out <= ROM(to_integer(unsigned(address)));
end process;

Example

This example shows a simple 4-word ROM with 8-bit data. The ROM data is fixed and read-only. The address input selects which word to output on data_out.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rom_example is
  port(
    address : in std_logic_vector(1 downto 0);
    data_out : out std_logic_vector(7 downto 0)
  );
end rom_example;

architecture behavioral of rom_example is
  type rom_type is array (0 to 3) of std_logic_vector(7 downto 0);
  constant ROM : rom_type := (
    0 => "00000001",
    1 => "00000010",
    2 => "00000100",
    3 => "00001000"
  );
begin
  process(address)
  begin
    data_out <= ROM(to_integer(unsigned(address)));
  end process;
end behavioral;

Output

When address = "00", data_out = "00000001"
When address = "01", data_out = "00000010"
When address = "10", data_out = "00000100"
When address = "11", data_out = "00001000"

Common Pitfalls

Common mistakes when modeling ROM in VHDL include:

• Using signal instead of constant for ROM data, which allows unintended modification.
• Not converting the std_logic_vector address to an integer before indexing the ROM array.
• Forgetting to include the numeric_std library for conversion functions.
• Using a variable inside a process for ROM data, which is not synthesizable.

vhdl

-- Wrong way: Using signal for ROM data
signal ROM : rom_type := (
  0 => "00000001",
  1 => "00000010",
  2 => "00000100",
  3 => "00001000"
);

-- Right way: Use constant for ROM data
constant ROM : rom_type := (
  0 => "00000001",
  1 => "00000010",
  2 => "00000100",
  3 => "00001000"
);

Quick Reference

Tips for modeling ROM in VHDL:

• Use constant arrays to store fixed ROM data.
• Convert address inputs from std_logic_vector to integer using to_integer(unsigned(address)).
• Use a process or with-select statement to assign output data.
• Include ieee.numeric_std library for conversions.

Key Takeaways

Model ROM as a constant array with fixed data values in VHDL.

Use address input converted to integer to index the ROM array.

Avoid using signals or variables for ROM data to keep it read-only.

Include ieee.numeric_std for address conversions.

Use a process or with-select to output ROM data based on address.