How to Write Asynchronous Reset in VHDL: Syntax and Example

In VHDL, an asynchronous reset is implemented by checking the reset signal in the sensitivity list and inside the process before the clock edge. Use an if reset = '1' then condition before the clock edge to reset signals immediately when reset is asserted.

Syntax

The asynchronous reset is written inside a process block with the reset signal included in the sensitivity list. The reset condition is checked first, outside the clock edge condition, so it triggers immediately when reset is active.

• process(clk, reset): sensitivity list includes clock and reset.
• if reset = '1' then: asynchronous reset condition.
• elsif rising_edge(clk) then: normal synchronous logic on clock edge.

vhdl

process(clk, reset)
begin
  if reset = '1' then
    -- reset signals here
  elsif rising_edge(clk) then
    -- normal operation
  end if;
end process;

Example

This example shows a simple 4-bit counter with an asynchronous active-high reset. When reset is '1', the counter resets immediately to zero, regardless of the clock. Otherwise, it increments on each rising clock edge.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity async_reset_counter is
  port(
    clk   : in std_logic;
    reset : in std_logic;
    count : out unsigned(3 downto 0)
  );
end entity;

architecture rtl of async_reset_counter is
  signal cnt : unsigned(3 downto 0) := (others => '0');
begin
  process(clk, reset)
  begin
    if reset = '1' then
      cnt <= (others => '0');  -- asynchronous reset
    elsif rising_edge(clk) then
      cnt <= cnt + 1;
    end if;
  end process;

  count <= cnt;
end architecture;

Common Pitfalls

Common mistakes when writing asynchronous resets include:

• Not including the reset signal in the process sensitivity list, so reset changes do not trigger the process immediately.
• Placing the reset condition inside the clock edge check, making the reset synchronous instead of asynchronous.
• Using active-low reset but checking for reset = '1' instead of reset = '0'.

Correct asynchronous reset must be checked before the clock edge condition and must be in the sensitivity list.

vhdl

process(clk)  -- wrong: reset missing in sensitivity list
begin
  if rising_edge(clk) then
    if reset = '1' then  -- wrong: reset inside clock edge
      cnt <= (others => '0');
    else
      cnt <= cnt + 1;
    end if;
  end if;
end process;

-- Correct version:
process(clk, reset)
begin
  if reset = '1' then
    cnt <= (others => '0');
  elsif rising_edge(clk) then
    cnt <= cnt + 1;
  end if;
end process;

Quick Reference

• Include reset in the process sensitivity list.
• Check reset condition before clock edge.
• Use if reset = '1' then for active-high reset or if reset = '0' then for active-low reset.
• Reset logic runs immediately when reset is asserted.

Key Takeaways

Always include the reset signal in the process sensitivity list for asynchronous reset.

Check the reset condition before the clock edge inside the process.

Use the correct active level ('1' or '0') matching your reset signal polarity.

Asynchronous reset triggers immediately, independent of the clock.

Avoid placing reset logic inside the clock edge condition to keep it asynchronous.