How to Use Generate Statement in VHDL: Syntax and Examples

In VHDL, the generate statement is used to create repeated or conditional hardware structures by generating multiple instances of code blocks. It works with for loops or if conditions inside an architecture to simplify designs and avoid manual duplication.

Syntax

The generate statement in VHDL can be used in two main forms: for-generate and if-generate. The for-generate repeats a block of code for a range of values, while the if-generate conditionally includes code based on a boolean expression.

• for-generate: repeats hardware blocks for each index in a range.
• if-generate: includes hardware blocks only if a condition is true.

vhdl

gen_label: for i in 0 to N generate
    -- hardware description using i
end generate;

cond_label: if condition generate
    -- hardware description if condition is true
end generate;

Example

This example shows how to use a for-generate to create 4 identical AND gates connecting bits of two 4-bit vectors.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity and_array is
    port(
        a, b : in std_logic_vector(3 downto 0);
        y    : out std_logic_vector(3 downto 0)
    );
end and_array;

architecture rtl of and_array is
begin
    and_gen: for i in 0 to 3 generate
    begin
        y(i) <= a(i) and b(i);
    end generate and_gen;
end rtl;

Common Pitfalls

Common mistakes when using generate include:

• Forgetting to label the generate block, which is required.
• Using variables or signals incorrectly inside the generate block.
• Trying to use generate outside an architecture or process.
• Misunderstanding that generate is elaboration-time code, not runtime.

Always ensure the generate label is unique and the syntax matches the VHDL standard.

vhdl

wrong_gen: for i in 0 to 3 loop  -- Incorrect: 'loop' used instead of 'generate'
    y(i) <= a(i) and b(i);
end loop;

correct_gen: for i in 0 to 3 generate
    y(i) <= a(i) and b(i);
end generate correct_gen;

Quick Reference

Feature	Description	Example
for-generate	Repeats code for a range of values	gen_label: for i in 0 to 3 generate ... end generate;
if-generate	Includes code conditionally	cond_label: if (enable = '1') generate ... end generate;
Label	Required name for generate block	gen_label:
Scope	Used inside architecture or block	architecture rtl of ... begin ... end;

Key Takeaways

Use generate to create repeated or conditional hardware blocks in VHDL.

Always label your generate blocks uniquely to avoid syntax errors.

Use for-generate for loops and if-generate for conditional code inclusion.

Generate statements run at elaboration time, not during simulation or hardware operation.

Place generate statements inside architectures or blocks, never outside.