VHDL Code for 4 Bit Down Counter: Syntax and Example

A 4 bit down counter in VHDL counts down from 15 to 0 using a clock and reset signal. Use a process triggered by the clock edge to decrement the counter value stored in a std_logic_vector(3 downto 0). Reset sets the counter back to 15.

Syntax

The basic syntax for a 4 bit down counter in VHDL includes a process block sensitive to the clock and reset signals. Inside, use an if statement to check for reset and set the counter to 15. On each rising clock edge, decrement the counter value.

• entity: Defines inputs and outputs.
• architecture: Contains the counter logic.
• process: Runs on clock and reset changes.
• if reset = '1': Resets counter to 15.
• elsif rising_edge(clk): Decrements counter.

vhdl

entity DownCounter4Bit is
    Port (
        clk   : in  std_logic;
        reset : in  std_logic;
        q     : out std_logic_vector(3 downto 0)
    );
end DownCounter4Bit;

architecture Behavioral of DownCounter4Bit is
    signal count : std_logic_vector(3 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= "1111"; -- 15 in binary
        elsif rising_edge(clk) then
            count <= std_logic_vector(unsigned(count) - 1);
        end if;
    end process;
    q <= count;
end Behavioral;

Example

This example shows a complete 4 bit down counter that starts at 15 and counts down to 0 on each clock pulse. When reset is high, the counter resets to 15 immediately.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DownCounter4Bit is
    Port (
        clk   : in  std_logic;
        reset : in  std_logic;
        q     : out std_logic_vector(3 downto 0)
    );
end DownCounter4Bit;

architecture Behavioral of DownCounter4Bit is
    signal count : std_logic_vector(3 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= "1111"; -- 15
        elsif rising_edge(clk) then
            if count = "0000" then
                count <= "1111"; -- wrap around to 15
            else
                count <= std_logic_vector(unsigned(count) - 1);
            end if;
        end if;
    end process;
    q <= count;
end Behavioral;

Output

On each rising clock edge, output q counts down from 1111 (15) to 0000 (0) and then wraps back to 1111.

Common Pitfalls

Common mistakes when writing a 4 bit down counter in VHDL include:

• Not using unsigned conversion before arithmetic, causing errors.
• Forgetting to handle the wrap-around from 0 back to 15.
• Not including reset in the sensitivity list of the process.
• Using if clk = '1' instead of rising_edge(clk) which is the recommended style.

vhdl

Wrong way:
process(clk)
begin
    if clk = '1' then -- Incorrect edge detection
        count <= std_logic_vector(unsigned(count) - 1);
    end if;
end process;

Right way:
process(clk, reset)
begin
    if reset = '1' then
        count <= "1111";
    elsif rising_edge(clk) then
        count <= std_logic_vector(unsigned(count) - 1);
    end if;
end process;

Quick Reference

Remember these key points for a 4 bit down counter in VHDL:

• Use std_logic_vector(3 downto 0) for 4 bits.
• Convert to unsigned before subtracting.
• Use rising_edge(clk) for clock detection.
• Reset sets counter to 15 ("1111").
• Handle wrap-around from 0 to 15 if needed.

Key Takeaways

Use rising_edge(clk) and include reset in the process sensitivity list.

Convert std_logic_vector to unsigned before arithmetic operations.

Reset the counter to 15 ("1111") to start counting down.

Handle wrap-around from 0 back to 15 to avoid underflow.

Always assign the counter signal to the output port.