What is Delta Delay in VHDL: Explanation and Example

In VHDL, delta delay is an infinitesimally small simulation time step used to order events that happen at the same simulation time. It allows the simulator to process signal updates in a precise sequence without advancing real simulation time.

How It Works

Think of delta delay as a tiny invisible step that the VHDL simulator uses to organize events happening at the exact same time. Imagine you have a group of friends trying to speak at once; the delta delay helps the simulator decide who talks first, second, and so on, even though the clock time doesn't move forward.

In VHDL simulation, time moves forward in discrete steps, but sometimes multiple signal changes need to happen 'at once'. The delta delay lets the simulator handle these changes in a strict order by inserting these tiny steps, ensuring signals update correctly and sequentially without increasing the actual simulation time.

Example

This example shows two signals assigned in a process. The second signal assignment sees the first signal's new value only after a delta delay, demonstrating how updates are ordered.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity delta_delay_example is
end entity delta_delay_example;

architecture behavior of delta_delay_example is
  signal a : std_logic := '0';
  signal b : std_logic := '0';
begin
  process
  begin
    a <= '1';  -- This assignment happens at current simulation time
    b <= a;    -- This reads old value of 'a' because 'a' update is delayed by delta
    wait for 10 ns;
    report "a = " & a & ", b = " & b;
    wait;
  end process;
end architecture behavior;

Output

a = 1, b = 0

When to Use

Delta delay is not something you explicitly code but is a fundamental part of VHDL simulation. It is important when you want to understand how signal assignments inside processes behave within the same simulation time step.

Use this knowledge when debugging signal updates or designing circuits where the order of signal changes matters, such as in combinational logic or feedback loops. It helps explain why some signals appear to update one step later than others even without real time passing.

Key Points

• Delta delay is an infinitesimally small simulation step used to order events at the same time.
• It ensures signal updates happen in a defined sequence without advancing simulation time.
• Signal assignments in VHDL processes take effect after a delta delay.
• Understanding delta delay helps debug timing and signal update issues in simulation.

Key Takeaways

Delta delay orders signal updates occurring at the same simulation time without advancing time.

Signal assignments inside processes take effect after a delta delay, not immediately.

Delta delay is essential for correct simulation of sequential signal changes.

Understanding delta delay helps explain signal behavior and timing in VHDL simulations.