Moore Machine in VHDL: Definition, Example, and Usage

A Moore machine in VHDL is a type of finite state machine where the outputs depend only on the current state, not on the inputs. It is modeled by defining states and output signals that change only when the state changes, making it predictable and easy to design.

How It Works

A Moore machine works like a vending machine that shows a fixed display depending on what step it is in, regardless of what button you press at that moment. In VHDL, this means the output signals are tied directly to the current state, not the inputs.

Think of it as a traffic light controller: the light color depends only on the current state (red, green, yellow), not on the cars waiting. The machine changes state based on inputs like timers or sensors, but the output (light color) is stable and only changes when the state changes.

This separation makes the design simpler and less prone to glitches because outputs don’t change immediately with inputs but only after a state transition.

Example

This example shows a simple Moore machine in VHDL that cycles through three states and outputs a 2-bit code depending on the state.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity moore_machine is
    Port (
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        output_signal : out STD_LOGIC_VECTOR(1 downto 0)
    );
end moore_machine;

architecture Behavioral of moore_machine is
    type state_type is (S0, S1, S2);
    signal current_state, next_state : state_type;
begin
    -- State register
    process(clk, reset)
    begin
        if reset = '1' then
            current_state <= S0;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    -- Next state logic
    process(current_state)
    begin
        case current_state is
            when S0 => next_state <= S1;
            when S1 => next_state <= S2;
            when S2 => next_state <= S0;
            when others => next_state <= S0;
        end case;
    end process;

    -- Output logic depends only on current state (Moore output)
    process(current_state)
    begin
        case current_state is
            when S0 => output_signal <= "00";
            when S1 => output_signal <= "01";
            when S2 => output_signal <= "10";
            when others => output_signal <= "00";
        end case;
    end process;
end Behavioral;

Output

On each clock cycle, output_signal cycles through 00, 01, 10, then back to 00, repeating.

When to Use

Use a Moore machine in VHDL when you want outputs that are stable and change only at state transitions. This is helpful in designs where output glitches must be avoided, such as control units, traffic lights, or simple protocol handlers.

Moore machines are easier to debug because outputs depend only on states, making behavior more predictable. They are ideal when outputs should not react immediately to input changes but only after a state change.

Key Points

• Outputs depend only on the current state, not inputs.
• Outputs change synchronously with state transitions.
• Design is simpler and less prone to glitches.
• Commonly used in control logic and sequential circuits.

Key Takeaways

A Moore machine's outputs depend only on its current state, ensuring stable outputs.

In VHDL, Moore machines separate state logic and output logic for clarity and reliability.

Use Moore machines when output stability and predictability are important.

Moore machines are easier to debug because outputs do not change asynchronously with inputs.