How to Set Up GHDL for VHDL Simulation and Compilation
To set up
ghdl for VHDL, first install it using your system's package manager or from source. Then, compile your VHDL files with ghdl -a, elaborate with ghdl -e, and run simulations using ghdl -r.Syntax
GHDL uses simple commands to work with VHDL files:
ghdl -a filename.vhdl: Analyze (compile) the VHDL source file.ghdl -e entity_name: Elaborate the design to prepare for simulation.ghdl -r entity_name: Run the simulation of the elaborated design.
Each step builds on the previous one to simulate your VHDL code.
bash
ghdl -a your_design.vhdl ghdl -e your_entity ghdl -r your_entity
Example
This example shows how to compile and simulate a simple VHDL AND gate using GHDL.
vhdl
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic
);
end entity and_gate;
architecture behavior of and_gate is
begin
y <= a and b;
end behavior;
-- Testbench
entity tb_and_gate is
end entity tb_and_gate;
architecture test of tb_and_gate is
signal a, b, y : std_logic := '0';
begin
uut: entity work.and_gate
port map(a => a, b => b, y => y);
process
begin
a <= '0'; b <= '0'; wait for 10 ns;
a <= '0'; b <= '1'; wait for 10 ns;
a <= '1'; b <= '0'; wait for 10 ns;
a <= '1'; b <= '1'; wait for 10 ns;
wait;
end process;
end test;Common Pitfalls
Common mistakes when setting up GHDL include:
- Not installing GHDL properly or missing dependencies.
- Forgetting to analyze all VHDL files before elaboration.
- Using the wrong entity name in the
ghdl -eandghdl -rcommands. - Not specifying the testbench entity for simulation.
Always check your entity names and ensure all files are compiled.
bash
Wrong: ghdl -e and_gate Right: ghdl -e tb_and_gate
Quick Reference
| Command | Purpose |
|---|---|
| ghdl -a file.vhdl | Analyze (compile) VHDL source file |
| ghdl -e entity_name | Elaborate design for simulation |
| ghdl -r entity_name | Run simulation |
| ghdl --help | Show help and options |
Key Takeaways
Install GHDL using your system package manager or from source before use.
Always analyze VHDL files with
ghdl -a before elaboration and simulation.Use the correct entity name, usually the testbench, when elaborating and running simulations.
Check for missing files or wrong entity names to avoid common errors.
Use
ghdl --help to explore more commands and options.