VHDL Code for Comparator: Syntax, Example, and Tips

A comparator in VHDL compares two inputs and outputs signals indicating if one is greater, equal, or less than the other. Use if-elsif-else statements inside a process block or concurrent signal assignments to implement it. The comparator outputs are usually std_logic signals showing comparison results.

Syntax

The basic syntax for a comparator in VHDL involves comparing two inputs using if-elsif-else inside a process block or using concurrent signal assignments. The inputs are usually std_logic_vector or unsigned types, and outputs are std_logic signals indicating comparison results.

• process: Defines a block that reacts to input changes.
• if-elsif-else: Checks conditions to compare inputs.
• outputs: Signals set to '1' or '0' based on comparison.

vhdl

process(a, b)
begin
  if a > b then
    gt <= '1';
    eq <= '0';
    lt <= '0';
  elsif a = b then
    gt <= '0';
    eq <= '1';
    lt <= '0';
  else
    gt <= '0';
    eq <= '0';
    lt <= '1';
  end if;
end process;

Example

This example shows a simple 4-bit comparator in VHDL. It compares two 4-bit inputs a and b and sets three outputs: gt (greater than), eq (equal), and lt (less than).

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity comparator_4bit is
  port(
    a  : in  unsigned(3 downto 0);
    b  : in  unsigned(3 downto 0);
    gt : out std_logic;
    eq : out std_logic;
    lt : out std_logic
  );
end comparator_4bit;

architecture Behavioral of comparator_4bit is
begin
  process(a, b)
  begin
    if a > b then
      gt <= '1';
      eq <= '0';
      lt <= '0';
    elsif a = b then
      gt <= '0';
      eq <= '1';
      lt <= '0';
    else
      gt <= '0';
      eq <= '0';
      lt <= '1';
    end if;
  end process;
end Behavioral;

Output

When run in simulation, outputs gt, eq, lt will be '1' or '0' depending on whether input a is greater than, equal to, or less than input b.

Common Pitfalls

Common mistakes when writing VHDL comparators include:

• Using std_logic_vector without conversion to unsigned or signed for numeric comparison.
• Forgetting to include all input signals in the process sensitivity list, causing simulation mismatches.
• Assigning multiple outputs in different processes without proper synchronization.
• Not handling the equality case explicitly, which can cause incorrect outputs.

vhdl

Wrong way:
process(a, b)
begin
  if a > b then
    gt <= '1';
  elsif a = b then
    eq <= '1';
  end if;
end process;

Right way:
process(a, b)
begin
  if a > b then
    gt <= '1'; eq <= '0'; lt <= '0';
  elsif a = b then
    gt <= '0'; eq <= '1'; lt <= '0';
  else
    gt <= '0'; eq <= '0'; lt <= '1';
  end if;
end process;

Quick Reference

Concept	Description
Inputs	Use unsigned or signed types for numeric comparison
Process Sensitivity	Include all inputs in sensitivity list
Comparison Operators	Use >, =, < for comparing unsigned/signed
Outputs	Set all output signals explicitly in all cases
Equality Case	Always handle equality explicitly to avoid errors

Key Takeaways

Use unsigned or signed types for numeric comparison in VHDL comparators.

Always include all input signals in the process sensitivity list.

Explicitly handle greater than, equal, and less than cases in your code.

Assign all output signals in every branch to avoid latches or incorrect outputs.

Test your comparator with different input values to verify correct behavior.