VHDL Code for D Latch: Syntax, Example, and Tips

A D latch in VHDL can be coded using a process sensitive to the enable signal, where the output follows the input D only when enable is high. The basic structure uses an if statement inside a process to control when the latch updates its output.

Syntax

The D latch in VHDL is typically written inside a process block sensitive to the enable signal and the data input D. Inside, an if statement checks if enable is high, then assigns the input D to the output Q. Otherwise, Q holds its previous value.

• process(enable, D): Runs when enable or D changes.
• if enable = '1' then: Updates output when enabled.
• Q <= D;: Assigns input to output.
• else: Holds output stable.

vhdl

process(enable, D)
begin
  if enable = '1' then
    Q <= D;
  end if;
end process;

Example

This example shows a complete D latch entity and architecture. The latch updates output Q when enable is high, otherwise it holds the last value.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity d_latch is
  Port (
    D      : in  STD_LOGIC;
    enable : in  STD_LOGIC;
    Q      : out STD_LOGIC
  );
end d_latch;

architecture Behavioral of d_latch is
begin
  process(enable, D)
  begin
    if enable = '1' then
      Q <= D;
    end if;
  end process;
end Behavioral;

Output

When enable = '1', Q follows D; when enable = '0', Q holds previous value.

Common Pitfalls

Common mistakes include:

• Not including D in the process sensitivity list, which can cause simulation mismatches.
• Using a clock signal instead of enable, which turns the latch into a flip-flop.
• Forgetting that the latch is level-sensitive, so output changes whenever enable is high.

Correct sensitivity list and understanding level sensitivity are key.

vhdl

process(enable)  -- Incorrect: missing D in sensitivity list
begin
  if enable = '1' then
    Q <= D;
  end if;
end process;

-- Correct:
process(enable, D)
begin
  if enable = '1' then
    Q <= D;
  end if;
end process;

Quick Reference

Signal	Description
D	Data input to latch
enable	Control signal; when '1', latch updates output
Q	Output that follows D when enabled, holds value otherwise

Key Takeaways

A D latch updates output only when enable is high, holding value otherwise.

Include both enable and D in the process sensitivity list for correct simulation.

D latch is level-sensitive, not edge-triggered like flip-flops.

Use an if statement inside a process to control output assignment.

Avoid using clock signals for enable to keep latch behavior.