VHDL How to Convert Integer to std_logic_vector Easily

In VHDL, convert an integer to std_logic_vector by first converting the integer to unsigned using to_unsigned(integer_value, size) and then casting it to std_logic_vector with std_logic_vector(to_unsigned(integer_value, size)).

Examples

Input5, size=4

Output"0101"

Input10, size=8

Output"00001010"

Input0, size=3

Output"000"

How to Think About It

To convert an integer to std_logic_vector, first think about representing the integer as a binary number with a fixed number of bits. VHDL provides a way to convert integers to unsigned binary vectors, which can then be treated as std_logic_vector by casting. This approach ensures the integer fits the desired bit width.

Algorithm

1

Get the integer value and the desired bit width.

2

Convert the integer to an unsigned vector of the given size.

3

Cast the unsigned vector to std_logic_vector.

4

Use the resulting std_logic_vector in your design.

Code

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity int_to_slv is
end entity;

architecture behavior of int_to_slv is
    signal int_val : integer := 5;
    signal slv_val : std_logic_vector(3 downto 0);
begin
    process
    begin
        slv_val <= std_logic_vector(to_unsigned(int_val, slv_val'length));
        report "Converted std_logic_vector: " & slv_val;
        wait;
    end process;
end architecture;

Output

Converted std_logic_vector: 0101

Dry Run

Let's trace converting integer 5 to std_logic_vector of size 4.

1

Input integer and size

int_val = 5, size = 4

2

Convert integer to unsigned

to_unsigned(5, 4) = "0101"

3

Cast unsigned to std_logic_vector

std_logic_vector(to_unsigned(5, 4)) = "0101"

Step	Value
Input integer	5
Unsigned vector	0101
std_logic_vector	0101

Why This Works

Step 1: Integer to unsigned conversion

The to_unsigned function converts the integer into a binary vector of a fixed size, representing the number in binary.

Step 2: Casting to std_logic_vector

Since to_unsigned returns an unsigned type, casting it to std_logic_vector allows it to be used where std_logic_vector is required.

Alternative Approaches

Using std_logic_vector with std_logic_arith package

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity int_to_slv_alt is
end entity;

architecture behavior of int_to_slv_alt is
    signal int_val : integer := 5;
    signal slv_val : std_logic_vector(3 downto 0);
begin
    process
    begin
        slv_val <= conv_std_logic_vector(int_val, slv_val'length);
        report "Converted std_logic_vector: " & slv_val;
        wait;
    end process;
end architecture;

This uses the older std_logic_arith package which is less standard and not recommended for new designs.

Complexity: O(1) time, O(n) space

Time Complexity

Conversion is a direct mapping of integer bits to vector bits, so it runs in constant time.

Space Complexity

Requires space proportional to the bit width of the output vector.

Which Approach is Fastest?

Using to_unsigned from numeric_std is standard and efficient; older packages may add overhead or compatibility issues.

Approach	Time	Space	Best For
to_unsigned + std_logic_vector cast	O(1)	O(n)	Standard, modern designs
conv_std_logic_vector (std_logic_arith)	O(1)	O(n)	Legacy code, older tools