VHDL Code for SISO Shift Register: Syntax and Example

A SISO (Serial-In Serial-Out) shift register in VHDL can be created using a process triggered by a clock edge that shifts input data through a register chain. Use std_logic_vector to hold bits and shift them on each clock cycle with a simple assignment inside a process block.

Syntax

The basic syntax for a SISO shift register in VHDL involves declaring a std_logic_vector signal to hold the bits and a process block sensitive to the clock. Inside the process, on the rising edge of the clock, the register shifts its bits and loads the new input bit.

• clk: Clock signal triggering the shift.
• reset: Optional asynchronous reset to clear the register.
• data_in: Serial input bit to be shifted in.
• shift_reg: The register holding the bits as a vector.

vhdl

process(clk, reset)
begin
  if reset = '1' then
    shift_reg <= (others => '0');
  elsif rising_edge(clk) then
    shift_reg <= shift_reg(shift_reg'length-2 downto 0) & data_in;
  end if;
end process;

Example

This example shows a 4-bit SISO shift register with synchronous reset. On each rising clock edge, the register shifts left and the new bit enters at the right end.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity siso_shift_register is
  Port (
    clk      : in  std_logic;
    reset    : in  std_logic;
    data_in  : in  std_logic;
    data_out : out std_logic
  );
end siso_shift_register;

architecture Behavioral of siso_shift_register is
  signal shift_reg : std_logic_vector(3 downto 0) := (others => '0');
begin
  process(clk, reset)
  begin
    if reset = '1' then
      shift_reg <= (others => '0');
    elsif rising_edge(clk) then
      shift_reg <= shift_reg(2 downto 0) & data_in;
    end if;
  end process;

  data_out <= shift_reg(3);
end Behavioral;

Output

On each clock cycle, the 4-bit register shifts left, outputting the oldest bit at data_out.

Common Pitfalls

Common mistakes include:

• Not using rising_edge(clk) for clock detection, which can cause simulation mismatches.
• Forgetting to reset the register, leading to unknown initial values.
• Incorrect slicing of the vector when shifting, causing data loss or wrong bit order.
• Assigning signals outside the process incorrectly, which can cause synthesis errors.

vhdl

Wrong way:
process(clk)
begin
  if clk = '1' then  -- Incorrect clock edge detection
    shift_reg <= shift_reg(2 downto 0) & data_in;
  end if;
end process;

Right way:
process(clk)
begin
  if rising_edge(clk) then
    shift_reg <= shift_reg(2 downto 0) & data_in;
  end if;
end process;

Quick Reference

Term	Description
clk	Clock input signal triggering shifts
reset	Asynchronous or synchronous reset to clear register
data_in	Serial input bit to shift into register
shift_reg	Internal register holding bits as std_logic_vector
rising_edge(clk)	Preferred clock edge detection method
shift_reg(2 downto 0) & data_in	Shifts bits left and inserts new bit at right

Key Takeaways

Use a process with rising_edge(clk) to shift bits in a SISO register.

Always reset the shift register to avoid unknown initial states.

Shift the register vector correctly to maintain bit order.

Assign the output to the oldest bit in the register for serial output.

Avoid incorrect clock edge detection and vector slicing mistakes.