VHDL Code for Subtractor: Syntax, Example, and Tips

A subtractor in VHDL can be created using the - operator inside a process or concurrent assignment. You define inputs as std_logic_vector and convert them to unsigned or signed types for arithmetic subtraction, then assign the result back to an output vector.

Syntax

The basic syntax for a subtractor in VHDL involves declaring input and output ports as std_logic_vector. Inside a process or concurrent statement, convert inputs to unsigned or signed types to perform subtraction using the - operator. Then convert the result back to std_logic_vector for output.

• Inputs: Vectors representing numbers to subtract
• Output: Vector representing the subtraction result
• Conversion: Use unsigned() or signed() from numeric_std library
• Operation: Use - operator for subtraction

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity subtractor is
    port(
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Diff : out std_logic_vector(3 downto 0)
    );
end subtractor;

architecture Behavioral of subtractor is
begin
    process(A, B)
    begin
        Diff <= std_logic_vector(unsigned(A) - unsigned(B));
    end process;
end Behavioral;

Example

This example shows a 4-bit subtractor that subtracts input B from input A and outputs the difference on Diff. It uses the numeric_std library for safe arithmetic on vectors.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity subtractor is
    port(
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Diff : out std_logic_vector(3 downto 0)
    );
end subtractor;

architecture Behavioral of subtractor is
begin
    process(A, B)
    begin
        Diff <= std_logic_vector(unsigned(A) - unsigned(B));
    end process;
end Behavioral;

Output

When inputs A="1010" (decimal 10) and B= "0011" (decimal 3), output Diff= "0111" (decimal 7).

Common Pitfalls

Common mistakes when writing a subtractor in VHDL include:

• Not using numeric_std library and trying to subtract std_logic_vector directly, which causes errors.
• Ignoring signed vs unsigned types, which can cause wrong results if negative numbers are involved.
• Not converting the result back to std_logic_vector before assigning to output.
• Forgetting to include all inputs in the sensitivity list of the process.

vhdl

library ieee;
use ieee.std_logic_1164.all;
-- Missing numeric_std causes error
entity wrong_subtractor is
    port(
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Diff : out std_logic_vector(3 downto 0)
    );
end wrong_subtractor;

architecture Behavioral of wrong_subtractor is
begin
    -- This will cause a compilation error
    process(A, B)
    begin
        Diff <= A - B; -- Wrong: std_logic_vector cannot be subtracted directly
    end process;
end Behavioral;

-- Correct way:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

architecture Fixed of wrong_subtractor is
begin
    process(A, B)
    begin
        Diff <= std_logic_vector(unsigned(A) - unsigned(B));
    end process;
end Fixed;

Quick Reference

Tips for writing a subtractor in VHDL:

• Always include ieee.numeric_std for arithmetic operations.
• Convert std_logic_vector inputs to unsigned or signed before subtracting.
• Convert the subtraction result back to std_logic_vector for output.
• Use a process with all inputs in the sensitivity list or concurrent assignment.

Key Takeaways

Use ieee.numeric_std library to perform subtraction on std_logic_vector inputs.

Convert inputs to unsigned or signed types before subtracting and convert result back to std_logic_vector.

Include all input signals in the process sensitivity list to ensure correct updates.

Avoid subtracting std_logic_vector directly without conversion to prevent errors.

Use a process or concurrent assignment for clean and readable subtractor code.