How to Use Record in VHDL: Syntax and Examples

In VHDL, a record groups multiple related signals or variables into one composite type. You define a record type with named fields, then declare signals or variables of that type to organize data cleanly and access fields with dot notation.

Syntax

A record type is defined using the type keyword followed by the record name and its fields inside record ... end record;. Each field has a name and a type. After defining the type, you declare signals or variables of that record type.

Example parts:

• type: declares a new record type
• record ... end record;: groups fields
• field_name : type;: defines each field
• signal/variable: declares an instance of the record
• dot notation: access fields like record_instance.field_name

vhdl

type MyRecord is record
    field1 : std_logic;
    field2 : integer;
end record;

signal rec_signal : MyRecord;

Example

This example shows how to define a record type, declare a signal of that type, assign values to its fields, and use them in a process.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity record_example is
    port(
        clk : in std_logic;
        out_signal : out std_logic
    );
end entity;

architecture Behavioral of record_example is
    type StatusRecord is record
        ready : std_logic;
        count : integer;
    end record;

    signal status : StatusRecord := (ready => '0', count => 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            status.ready <= '1';
            status.count <= status.count + 1;
            out_signal <= status.ready;
        end if;
    end process;
end Behavioral;

Common Pitfalls

Common mistakes when using records in VHDL include:

• Forgetting to define the record type before declaring signals or variables.
• Trying to assign a whole record at once without matching all fields.
• Using incorrect dot notation or misspelling field names.
• Not initializing record fields, which can cause simulation warnings.

Always initialize records and use correct field names to avoid errors.

vhdl

type MyRecord is record
    a : std_logic;
    b : integer;
end record;

-- Wrong: missing type definition before signal declaration
-- signal rec : UndefinedRecord;

-- Wrong: assigning incomplete record
-- rec.a <= '1';
-- rec.b <= 5;
-- rec <= (a => '1'); -- Missing field b

-- Right:
signal rec : MyRecord := (a => '0', b => 0);

Quick Reference

Concept	Description	Example
Define Record Type	Create a new record type with named fields	type MyRec is record a: std_logic; b: integer; end record;
Declare Signal/Variable	Use the record type to declare signals or variables	signal rec_sig : MyRec;
Assign Fields	Assign values to individual fields using dot notation	rec_sig.a <= '1'; rec_sig.b <= 10;
Initialize Record	Set initial values when declaring	signal rec_sig : MyRec := (a => '0', b => 0);
Access Fields	Use dot notation to read or write fields	x <= rec_sig.a;

Key Takeaways

Define a record type before declaring signals or variables of that type.

Use dot notation to access or assign individual fields in a record.

Always initialize record fields to avoid simulation warnings.

Records help organize related signals into one grouped data structure.

Check field names carefully to avoid syntax errors.