How to Use Generic in VHDL: Syntax and Example

In VHDL, generic allows you to define parameters for components or entities that can be set when the component is instantiated. This makes your design flexible by letting you customize values like widths or delays without changing the code inside the component.

Syntax

The generic clause is declared inside an entity to define parameters. Each generic has a name, type, and optional default value. When you instantiate the entity, you can override these values.

Parts explained:

• generic: starts the generic declaration block.
• name: the parameter's identifier.
• type: data type like integer, std_logic_vector, etc.
• := default_value: optional default if no override is given.

vhdl

entity ExampleEntity is
  generic (
    WIDTH : integer := 8
  );
  port (
    input_signal : in std_logic_vector(WIDTH-1 downto 0);
    output_signal : out std_logic_vector(WIDTH-1 downto 0)
  );
end ExampleEntity;

Example

This example shows a simple VHDL entity using a generic to set the width of input and output signals. The architecture copies the input to the output. When instantiated, you can change WIDTH to handle different bus sizes.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity BusPass is
  generic (
    WIDTH : integer := 8
  );
  port (
    data_in  : in  std_logic_vector(WIDTH-1 downto 0);
    data_out : out std_logic_vector(WIDTH-1 downto 0)
  );
end BusPass;

architecture Behavioral of BusPass is
begin
  data_out <= data_in;
end Behavioral;

-- Instantiation example
-- signal input_bus : std_logic_vector(15 downto 0);
-- signal output_bus : std_logic_vector(15 downto 0);
--
-- U1: entity work.BusPass
--   generic map (WIDTH => 16)
--   port map (
--     data_in => input_bus,
--     data_out => output_bus
--   );

Common Pitfalls

Common mistakes when using generics include:

• Not providing a default value, which forces the user to always specify the generic.
• Mismatching generic types between entity and instantiation.
• Using generics inside the architecture without proper reference, causing synthesis errors.
• Trying to change generics at runtime (they are static and fixed at elaboration).

Example of wrong and right usage:

vhdl

-- Wrong: Missing generic map when WIDTH has no default
entity NoDefault is
  generic (WIDTH : integer);
  port (data_in : in std_logic_vector(WIDTH-1 downto 0));
end NoDefault;

-- Instantiation missing generic map causes error
-- U2: entity work.NoDefault
--   generic map (WIDTH => 8)
--   port map (data_in => some_signal);

-- Right: Provide generic map or default value
entity WithDefault is
  generic (WIDTH : integer := 8);
  port (data_in : in std_logic_vector(WIDTH-1 downto 0));
end WithDefault;

-- Instantiation uses default or overrides
-- U3: entity work.WithDefault
--   generic map (WIDTH => 16)
--   port map (data_in => some_signal);

Quick Reference

Summary tips for using generics in VHDL:

• Declare generics inside the entity block.
• Always specify type and optionally a default value.
• Override generics during instantiation with generic map.
• Generics are static and cannot change during simulation runtime.
• Use generics to make reusable and configurable components.

Key Takeaways

Generics in VHDL define parameters to customize entities at instantiation.

Always declare generics with a type and optionally a default value.

Override generics using generic map when instantiating components.

Generics are static and set before simulation or synthesis starts.

Using generics makes your VHDL code flexible and reusable.