VHDL Code for Sequence Detector 1011: Complete Example

A sequence detector for pattern 1011 in VHDL can be implemented using a finite state machine that checks input bits one by one. The code uses states to track progress and outputs a signal when the sequence is detected.

Syntax

The sequence detector uses a process block triggered by the clock and reset signals. Inside, a case statement defines states representing how much of the sequence has been matched. The input bit is checked each clock cycle to move between states. When the full sequence is detected, an output signal is set.

Key parts:

• type state_type is (S0, S1, S2, S3, S4); defines states.
• signal current_state, next_state : state_type; hold the current and next states.
• process(clk, reset) updates states on clock edge or reset.
• process(current_state, input_bit) decides next state based on input.
• output_signal is set high when sequence 1011 is detected.

vhdl

type state_type is (S0, S1, S2, S3, S4);
signal current_state, next_state : state_type;

process(clk, reset) is
begin
  if reset = '1' then
    current_state <= S0;
  elsif rising_edge(clk) then
    current_state <= next_state;
  end if;
end process;

process(current_state, input_bit) is
begin
  case current_state is
    when S0 =>
      if input_bit = '1' then
        next_state <= S1;
      else
        next_state <= S0;
      end if;
    when S1 =>
      if input_bit = '0' then
        next_state <= S2;
      else
        next_state <= S1;
      end if;
    when S2 =>
      if input_bit = '1' then
        next_state <= S3;
      else
        next_state <= S0;
      end if;
    when S3 =>
      if input_bit = '1' then
        next_state <= S4;
      else
        next_state <= S2;
      end if;
    when S4 =>
      next_state <= S0;
  end case;
end process;

output_signal <= '1' when current_state = S4 else '0';

Example

This example shows a full VHDL code for a sequence detector that detects the pattern 1011. It uses a synchronous reset and outputs 1 when the sequence is found. The detector can overlap sequences.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity seq_detector_1011 is
  Port (
    clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    input_bit : in STD_LOGIC;
    detected : out STD_LOGIC
  );
end seq_detector_1011;

architecture Behavioral of seq_detector_1011 is
  type state_type is (S0, S1, S2, S3, S4);
  signal current_state, next_state : state_type;
begin
  process(clk, reset) is
  begin
    if reset = '1' then
      current_state <= S0;
    elsif rising_edge(clk) then
      current_state <= next_state;
    end if;
  end process;

  process(current_state, input_bit) is
  begin
    case current_state is
      when S0 =>
        if input_bit = '1' then
          next_state <= S1;
        else
          next_state <= S0;
        end if;
      when S1 =>
        if input_bit = '0' then
          next_state <= S2;
        else
          next_state <= S1;
        end if;
      when S2 =>
        if input_bit = '1' then
          next_state <= S3;
        else
          next_state <= S0;
        end if;
      when S3 =>
        if input_bit = '1' then
          next_state <= S4;
        else
          next_state <= S2;
        end if;
      when S4 =>
        next_state <= S0;
    end case;
  end process;

  detected <= '1' when current_state = S4 else '0';
end Behavioral;

Output

The output signal 'detected' goes high ('1') for one clock cycle when the input sequence 1011 is detected.

Common Pitfalls

Common mistakes when writing a sequence detector include:

• Not handling overlapping sequences properly, causing missed detections.
• Forgetting to reset the state machine, which can cause unpredictable behavior.
• Incorrect state transitions that do not follow the sequence pattern.
• Setting the output signal incorrectly, either too long or too short.

Always test with input sequences that include overlapping patterns like 1011011 to verify correct detection.

vhdl

/* Wrong: Not resetting state machine */
process(clk) is
begin
  if rising_edge(clk) then
    current_state <= next_state; -- no reset condition
  end if;
end process;

/* Right: Include reset */
process(clk, reset) is
begin
  if reset = '1' then
    current_state <= S0;
  elsif rising_edge(clk) then
    current_state <= next_state;
  end if;
end process;

Quick Reference

Tips for writing a sequence detector in VHDL:

• Use a clear state machine with named states for each step of the sequence.
• Include a synchronous reset to initialize the state.
• Check input bits on each clock cycle to move between states.
• Set the output high only when the full sequence is detected.
• Test with overlapping sequences to ensure reliability.

Key Takeaways

Use a finite state machine to track progress through the sequence 1011.

Always include a reset to initialize the state machine safely.

Handle overlapping sequences by carefully designing state transitions.

Set the output signal high only when the full sequence is detected.

Test your design with various input patterns to ensure correct detection.