How to Generate Clock in VHDL Testbench: Simple Guide

To generate a clock in a VHDL testbench, create a process that toggles a std_logic signal at regular intervals using wait for statements. This simulates a clock by switching the signal between '0' and '1' repeatedly.

Syntax

Use a process block to toggle a clock signal. Inside the process, alternate the clock signal between '0' and '1' with wait for delays to set the clock period.

• clk : std_logic := '0'; declares the clock signal.
• process defines the clock toggling behavior.
• wait for 10 ns; sets half the clock period (for 50 MHz clock, 10 ns high and 10 ns low).

vhdl

signal clk : std_logic := '0';
process
begin
    clk <= '0';
    wait for 10 ns;
    clk <= '1';
    wait for 10 ns;
end process;

Example

This example shows a complete VHDL testbench that generates a 50 MHz clock signal by toggling clk every 10 ns. The clock runs for 100 ns in simulation.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity tb_clock is
end tb_clock;

architecture behavior of tb_clock is
    signal clk : std_logic := '0';
begin
    clock_process : process
    begin
        while now < 100 ns loop
            clk <= '0';
            wait for 10 ns;
            clk <= '1';
            wait for 10 ns;
        end loop;
        wait;
    end process clock_process;
end behavior;

Output

Simulation runs with clk toggling every 10 ns, producing a 50 MHz clock signal for 100 ns.

Common Pitfalls

Common mistakes when generating clocks in VHDL testbenches include:

• Not using wait statements inside the process, causing infinite loops or no toggling.
• Forgetting to initialize the clock signal before toggling.
• Using wait on clk; inside the clock generation process, which can cause simulation deadlock.
• Setting incorrect wait times, resulting in wrong clock frequency.

vhdl

wrong_clock_process : process
begin
    clk <= '0';
    clk <= '1'; -- No wait, toggles instantly
end process;

correct_clock_process : process
begin
    clk <= '0';
    wait for 10 ns;
    clk <= '1';
    wait for 10 ns;
end process;

Quick Reference

Concept	Description
Clock signal	A std_logic signal toggled between '0' and '1'
Process	Used to create the toggling behavior
Wait statement	Controls the clock period by delaying signal changes
Clock period	Sum of high and low wait times (e.g., 20 ns for 50 MHz)
Initialization	Set clock initial value before toggling

Key Takeaways

Generate a clock by toggling a std_logic signal inside a process with wait delays.

Use wait statements to control the clock period precisely.

Initialize the clock signal before starting the toggling process.

Avoid missing wait statements to prevent simulation issues.

Set wait times to match the desired clock frequency.