Resolution Function in VHDL: Definition and Usage

In VHDL, a resolution function is a special function used to decide the final value of a signal when multiple drivers assign different values to it. It combines these conflicting values into a single resolved value, ensuring correct signal behavior in designs with multiple sources.

How It Works

Imagine you have several friends trying to decide what movie to watch, but each suggests a different one. A resolution function acts like a mediator who listens to all suggestions and picks one final movie everyone agrees on. In VHDL, when multiple parts of a circuit try to drive a signal with different values, the resolution function combines these values into one final output.

This function is automatically called by VHDL when a signal has multiple drivers. It takes all the driven values as input and returns a single value that represents the combined effect. This is essential for signals like std_logic which can have multiple sources, such as buses or tri-state lines.

Example

This example shows a simple resolution function for a std_logic signal that resolves conflicts by prioritizing '1' over '0' and 'Z' (high impedance).

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Custom resolution function
function my_resolution_function(signal_vector: std_logic_vector) return std_logic is
  variable result: std_logic := 'Z';
begin
  for i in signal_vector'range loop
    if signal_vector(i) = '1' then
      result := '1';
      exit;
    elsif signal_vector(i) = '0' then
      if result /= '1' then
        result := '0';
      end if;
    end if;
  end loop;
  return result;
end function;

-- Example usage in a resolved signal type
subtype my_std_logic is std_logic;
type my_std_logic_resolved is resolved my_resolution_function;

-- Test entity
entity test_res_func is
end entity;

architecture behavior of test_res_func is
  signal sig: my_std_logic_resolved;
begin
  process
  begin
    sig <= 'Z';
    wait for 10 ns;
    sig <= '0';
    wait for 10 ns;
    sig <= '1';
    wait for 10 ns;
    wait;
  end process;
end behavior;

Output

At 0 ns: sig = Z
At 10 ns: sig = 0
At 20 ns: sig = 1

When to Use

Use a resolution function in VHDL when you have signals driven by multiple sources and you need to define how to combine their values. This is common in bus systems, tri-state buffers, or wired-AND/OR logic where multiple components share a signal line.

Without a resolution function, VHDL cannot decide the final signal value if drivers conflict, leading to simulation errors or incorrect hardware behavior. Defining a custom resolution function lets you control how conflicts are handled, such as prioritizing certain values or modeling specific electrical behaviors.

Key Points

• A resolution function combines multiple driven values on a signal into one final value.
• It is required for signals with multiple drivers, like std_logic.
• You can write custom resolution functions to define specific conflict rules.
• Resolution functions help simulate real hardware behavior accurately.

Key Takeaways

A resolution function resolves conflicting signal values from multiple drivers into one final value.

It is essential for signals like std_logic that can have multiple sources.

Custom resolution functions let you define how conflicts are handled in your design.

Without resolution functions, VHDL cannot simulate signals with multiple drivers correctly.