How to Use ModelSim for VHDL Simulation and Testing

To use ModelSim for VHDL, first compile your VHDL files using the vcom command, then simulate the design with vsim. You can run simulations, view waveforms, and check outputs interactively or via scripts.

Syntax

ModelSim uses simple commands to compile and simulate VHDL code:

• vcom [options] filename.vhd: Compiles VHDL source files.
• vsim [options] work.entity_name: Starts simulation of the compiled design.
• run [time]: Runs the simulation for a specified time.
• add wave *: Adds all signals to the waveform viewer.

These commands are used inside the ModelSim command prompt or script files.

shell

vcom my_design.vhd
vsim work.my_design
add wave *
run 100 ns

Example

This example shows how to compile and simulate a simple VHDL AND gate in ModelSim.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
    port(a, b: in std_logic; y: out std_logic);
end and_gate;

architecture behavior of and_gate is
begin
    y <= a and b;
end behavior;

-- Testbench
library ieee;
use ieee.std_logic_1164.all;

entity tb_and_gate is
end tb_and_gate;

architecture test of tb_and_gate is
    signal a, b, y: std_logic := '0';
begin
    uut: entity work.and_gate
        port map(a => a, b => b, y => y);

    process
    begin
        a <= '0'; b <= '0'; wait for 10 ns;
        a <= '0'; b <= '1'; wait for 10 ns;
        a <= '1'; b <= '0'; wait for 10 ns;
        a <= '1'; b <= '1'; wait for 10 ns;
        wait;
    end process;
end test;

Common Pitfalls

Common mistakes when using ModelSim for VHDL include:

• Not compiling all necessary files before simulation, causing errors.
• Forgetting to specify the correct entity name in the vsim command.
• Running simulation without adding signals to the waveform viewer, making debugging harder.
• Not running the simulation long enough to see expected behavior.

Always check compilation messages and simulation logs for errors.

shell

# Wrong: Missing compilation of testbench
vcom and_gate.vhd
vsim work.tb_and_gate  -- Error: tb_and_gate not compiled

# Right: Compile all files
vcom and_gate.vhd
vcom tb_and_gate.vhd
vsim work.tb_and_gate
add wave *
run 40 ns

Quick Reference

Command	Purpose
vcom filename.vhd	Compile VHDL source file
vsim work.entity_name	Start simulation of compiled design
add wave *	Add all signals to waveform viewer
run time	Run simulation for specified time (e.g., 100 ns)
quit	Exit ModelSim

Key Takeaways

Compile all VHDL files with vcom before simulating.

Use vsim with the correct entity name to start simulation.

Add signals to the waveform viewer to observe signal changes.

Run the simulation long enough to see the design behavior.

Check compilation and simulation logs for errors.