VHDL Code for Shift Register: Syntax and Example

A shift register in VHDL is a sequential circuit that shifts data bits on each clock cycle. You define it using a process triggered by a clock, updating a std_logic_vector signal by shifting bits left or right. The code typically includes a clock and reset signal to control the shifting operation.

Syntax

A shift register in VHDL uses a process block sensitive to the clock and optionally reset signals. Inside, you update a std_logic_vector signal by shifting bits left or right. The main parts are:

• Clock and reset signals: Control when shifting happens and when to clear the register.
• Shift register signal: A std_logic_vector holding the bits.
• Shift operation: Assigning the register to a shifted version of itself.

vhdl

process(clk, reset)
begin
  if reset = '1' then
    shift_reg <= (others => '0');
  elsif rising_edge(clk) then
    shift_reg <= shift_reg(shift_reg'length-2 downto 0) & data_in;
  end if;
end process;

Example

This example shows an 8-bit shift register that shifts bits in from data_in on each rising clock edge. It resets to all zeros when reset is high.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ShiftRegister is
  Port (
    clk      : in  std_logic;
    reset    : in  std_logic;
    data_in  : in  std_logic;
    q        : out std_logic_vector(7 downto 0)
  );
end ShiftRegister;

architecture Behavioral of ShiftRegister is
  signal shift_reg : std_logic_vector(7 downto 0) := (others => '0');
begin
  process(clk, reset)
  begin
    if reset = '1' then
      shift_reg <= (others => '0');
    elsif rising_edge(clk) then
      shift_reg <= shift_reg(6 downto 0) & data_in;
    end if;
  end process;

  q <= shift_reg;
end Behavioral;

Output

On each rising clock edge, the 8-bit register shifts left by one bit, inserting data_in at the least significant bit. When reset is '1', the register clears to 00000000.

Common Pitfalls

• Forgetting to include the reset condition causes the register to hold old data after power-up.
• Not using rising_edge(clk) can cause simulation mismatches or synthesis issues.
• Incorrect indexing in the shift operation can reverse the bit order or cause out-of-range errors.
• Assigning the shift register signal outside a clocked process leads to combinational logic, not a proper register.

vhdl

process(clk)
begin
  if clk = '1' then  -- Wrong: should use rising_edge(clk)
    shift_reg <= data_in & shift_reg(7 downto 1); -- Wrong shift direction
  end if;
end process;

-- Correct version:
process(clk)
begin
  if rising_edge(clk) then
    shift_reg <= shift_reg(6 downto 0) & data_in;
  end if;
end process;

Quick Reference

Remember these tips when writing a VHDL shift register:

• Use rising_edge(clk) for clock detection.
• Include an asynchronous or synchronous reset to initialize the register.
• Shift bits by slicing the vector and concatenating the new input.
• Keep the shift register signal inside a clocked process for proper sequential behavior.

Key Takeaways

Use a clocked process with rising_edge(clk) to implement shifting in VHDL.

Initialize the shift register with a reset signal to avoid unknown states.

Shift bits by slicing the vector and concatenating the new input bit.

Avoid combinational assignments for shift registers; use sequential logic.

Check bit indexing carefully to ensure correct shift direction.