VHDL Code for 4 Bit Adder: Syntax and Example

A 4 bit adder in VHDL adds two 4-bit binary numbers and outputs a 4-bit sum and a carry bit. You can write it using a process block or by instantiating four 1-bit full adders connected in series. The simplest way is to use the built-in unsigned type and the + operator for addition.

Syntax

The basic syntax for a 4 bit adder in VHDL involves declaring input and output ports, using the unsigned type for binary numbers, and performing addition with the + operator. The library ieee; and use ieee.numeric_std.all; lines are needed to use arithmetic on unsigned types.

• entity: Defines the input/output interface.
• architecture: Contains the logic for addition.
• unsigned: Data type for binary numbers.
• +: Operator to add unsigned numbers.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Adder4Bit is
    port(
        A : in unsigned(3 downto 0);
        B : in unsigned(3 downto 0);
        Sum : out unsigned(3 downto 0);
        CarryOut : out std_logic
    );
end Adder4Bit;

architecture Behavioral of Adder4Bit is
begin
    process(A, B)
        variable temp : unsigned(4 downto 0);
    begin
        temp := ('0' & A) + ('0' & B);
        Sum <= temp(3 downto 0);
        CarryOut <= temp(4);
    end process;
end Behavioral;

Example

This example shows a complete 4 bit adder that adds two 4-bit inputs A and B and outputs the 4-bit Sum and a CarryOut bit. It uses the unsigned type and a process block to perform addition.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Adder4Bit is
    port(
        A : in unsigned(3 downto 0);
        B : in unsigned(3 downto 0);
        Sum : out unsigned(3 downto 0);
        CarryOut : out std_logic
    );
end Adder4Bit;

architecture Behavioral of Adder4Bit is
begin
    process(A, B)
        variable temp : unsigned(4 downto 0);
    begin
        temp := ('0' & A) + ('0' & B);
        Sum <= temp(3 downto 0);
        CarryOut <= temp(4);
    end process;
end Behavioral;

Output

When simulated with inputs A="1010" (decimal 10) and B="0101" (decimal 5), the output Sum="1111" (decimal 15) and CarryOut='0'. For inputs A="1111" and B="0001", Sum="0000" and CarryOut='1'.

Common Pitfalls

Common mistakes when writing a 4 bit adder in VHDL include:

• Not using unsigned or signed types for arithmetic, which causes errors.
• Forgetting to include the numeric_std library.
• Ignoring the carry out bit by only assigning 4 bits to the sum.
• Using std_logic_vector directly without conversion, which does not support arithmetic.

Always convert std_logic_vector to unsigned before adding.

vhdl

library ieee;
use ieee.std_logic_1164.all;
-- Missing numeric_std causes errors

entity WrongAdder is
    port(
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sum : out std_logic_vector(3 downto 0);
        CarryOut : out std_logic
    );
end WrongAdder;

architecture Behavioral of WrongAdder is
begin
    -- This will cause an error because + is not defined for std_logic_vector
    Sum <= A + B;
end Behavioral;

-- Correct way:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity CorrectAdder is
    port(
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sum : out std_logic_vector(3 downto 0);
        CarryOut : out std_logic
    );
end CorrectAdder;

architecture Behavioral of CorrectAdder is
    signal A_unsigned, B_unsigned : unsigned(3 downto 0);
    signal temp : unsigned(4 downto 0);
begin
    A_unsigned <= unsigned(A);
    B_unsigned <= unsigned(B);
    temp <= ('0' & A_unsigned) + ('0' & B_unsigned);
    Sum <= std_logic_vector(temp(3 downto 0));
    CarryOut <= temp(4);
end Behavioral;

Quick Reference

• Use unsigned type for binary arithmetic.
• Include library ieee; and use ieee.numeric_std.all;.
• Concatenate a '0' bit to inputs to capture carry out.
• Use a 5-bit variable to hold sum and carry.
• Convert between std_logic_vector and unsigned as needed.

Key Takeaways

Use the ieee.numeric_std library and unsigned type for arithmetic in VHDL.

Concatenate a leading zero to inputs to handle carry out in 4 bit addition.

Convert std_logic_vector to unsigned before adding to avoid errors.

Always assign both sum bits and carry out bit to capture full addition result.

Test your adder with different inputs to verify correct sum and carry outputs.