What is Synthesis in VHDL: Definition and Examples

In VHDL, synthesis is the process of converting the written hardware description code into a physical hardware design like a gate-level circuit. It transforms the abstract VHDL code into a netlist that can be implemented on devices such as FPGAs or ASICs.

How It Works

Synthesis in VHDL works like translating a recipe into a finished dish. You write the recipe (the VHDL code) describing what you want, and synthesis tools convert this recipe into actual kitchen steps (hardware gates and connections) that a machine can follow.

The synthesis tool reads your VHDL code, understands the logic and structure, and then creates a detailed map of electronic components and their connections. This map is called a netlist, which can be used to build the physical circuit on chips like FPGAs or ASICs.

Think of synthesis as the bridge between your design ideas in code and the real hardware that performs those ideas.

Example

This simple VHDL example describes a 2-input AND gate. When synthesized, it will create a physical AND gate circuit.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    Y <= A and B;
end Behavioral;

Output

No runtime output; synthesis produces hardware netlist for an AND gate.

When to Use

Use synthesis when you want to turn your VHDL designs into real hardware circuits. It is essential for creating digital devices like processors, controllers, and communication hardware.

For example, if you design a custom logic circuit or a state machine in VHDL, synthesis tools help you implement it on an FPGA board for testing or production. It is also used in ASIC design to prepare the chip layout.

Key Points

• Synthesis converts VHDL code into a hardware netlist.
• It bridges the gap between design and physical hardware.
• Used for FPGA and ASIC hardware implementation.
• Requires writing synthesizable VHDL code.

Key Takeaways

Synthesis transforms VHDL code into a physical hardware design.

It produces a netlist used to build circuits on FPGAs or ASICs.

Only synthesizable VHDL code can be converted into hardware.

Synthesis is essential for turning digital designs into real devices.