How to Encode States in VHDL: Syntax and Examples

In VHDL, states are encoded using enumerated types or constants representing each state. You define a type listing all states, then use a signal of that type to hold the current state in your finite state machine.

Syntax

To encode states in VHDL, first declare an enumerated type listing all states. Then declare a signal of this type to hold the current state. Use a case statement to handle transitions.

• type: Defines all possible states.
• signal: Holds the current state value.
• case: Controls behavior based on the current state.

vhdl

type state_type is (IDLE, START, PROCESS, DONE);
signal current_state : state_type := IDLE;

process(clk)
begin
  if rising_edge(clk) then
    case current_state is
      when IDLE =>
        -- actions for IDLE
      when START =>
        -- actions for START
      when PROCESS =>
        -- actions for PROCESS
      when DONE =>
        -- actions for DONE
    end case;
  end if;
end process;

Example

This example shows a simple finite state machine with four states encoded using an enumerated type. The machine cycles through states on each clock rising edge.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity fsm_example is
  port(
    clk : in std_logic;
    reset : in std_logic;
    state_out : out std_logic_vector(1 downto 0)
  );
end fsm_example;

architecture Behavioral of fsm_example is
  type state_type is (IDLE, START, PROCESS, DONE);
  signal current_state : state_type := IDLE;
begin
  process(clk, reset)
  begin
    if reset = '1' then
      current_state <= IDLE;
    elsif rising_edge(clk) then
      case current_state is
        when IDLE =>
          current_state <= START;
        when START =>
          current_state <= PROCESS;
        when PROCESS =>
          current_state <= DONE;
        when DONE =>
          current_state <= IDLE;
      end case;
    end if;
  end process;

  -- Output encoded as 2-bit vector
  with current_state select
    state_out <= "00" when IDLE,
                 "01" when START,
                 "10" when PROCESS,
                 "11" when DONE;
end Behavioral;

Output

On each clock cycle, state_out cycles through 00, 01, 10, 11 representing IDLE, START, PROCESS, DONE states.

Common Pitfalls

Common mistakes when encoding states in VHDL include:

• Not initializing the state signal, causing undefined behavior.
• Using integers or std_logic_vector without clear mapping, making code harder to read.
• Forgetting to cover all states in the case statement, which can cause synthesis warnings.
• Mixing state encoding styles, leading to confusion.

vhdl

---- Wrong: Using integers without clear meaning
-- signal current_state : integer := 0;
-- process(clk)
-- begin
--   if rising_edge(clk) then
--     if current_state = 0 then
--       current_state <= 1;
--     end if;
--   end if;
-- end process;

---- Right: Use enumerated type for clarity

type state_type is (IDLE, START);
signal current_state : state_type := IDLE;

Quick Reference

Concept	Description	Example
Enumerated Type	Defines all states by name	type state_type is (IDLE, START, PROCESS, DONE);
State Signal	Holds current state value	signal current_state : state_type := IDLE;
State Transitions	Use case statement inside clocked process	case current_state is ... end case;
Output Encoding	Map states to output bits	with current_state select state_out <= "00" when IDLE;

Key Takeaways

Use enumerated types to clearly name and encode states in VHDL.

Always initialize the state signal to avoid undefined states.

Use a case statement inside a clocked process to manage state transitions.

Map states to output signals explicitly for clear encoding.

Avoid using raw integers or vectors without clear state definitions.