How to Use Assert in VHDL: Syntax and Examples

In VHDL, use the assert statement to check conditions during simulation and report messages if conditions fail. The syntax is assert condition report "message" severity level;, where you specify the condition, a message, and the severity level like note, warning, or error.

Syntax

The assert statement in VHDL checks a condition and reports a message if the condition is false. It has three parts:

• condition: A boolean expression to test.
• report message: A string message shown if the condition is false.
• severity level: The importance of the message, such as note, warning, error, or failure.

vhdl

assert condition report "message" severity level;

Example

This example shows how to use assert to check if a signal data_valid is true. If it is false, it reports a warning message during simulation.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity AssertExample is
end AssertExample;

architecture Behavioral of AssertExample is
  signal data_valid : boolean := false;
begin
  process
  begin
    -- Check if data_valid is true
    assert data_valid
      report "Data is not valid!" severity warning;
    wait for 10 ns;
    data_valid <= true;
    wait for 10 ns;
    assert data_valid
      report "Data is not valid!" severity warning;
    wait;
  end process;
end Behavioral;

Output

Warning: Data is not valid!

Common Pitfalls

Common mistakes when using assert in VHDL include:

• Forgetting the report keyword, which causes syntax errors.
• Not specifying a severity level, which is required.
• Using assert with conditions that never change, making the message always appear or never appear.
• Using assert in synthesis code, which is ignored by most synthesis tools and only works in simulation.

vhdl

-- Wrong usage: missing report and severity
-- assert data_valid;  -- This will cause syntax error

-- Correct usage:
assert data_valid report "Data invalid" severity error;

Quick Reference

Part	Description	Example
condition	Boolean expression to check	data_valid = true
report message	Message shown if condition is false	"Data invalid!"
severity	Level of message importance	warning, error, note, failure

Key Takeaways

Use assert to check conditions and report messages during simulation.

Always include report and severity keywords with assert.

Severity levels control how serious the message is and affect simulation behavior.

Assert statements are for simulation debugging and usually ignored in synthesis.

Write clear messages to help identify issues quickly during simulation.