VHDL Code for Clock Divider by 3: Simple Example and Explanation

A clock divider by 3 in VHDL can be implemented using a counter that counts clock pulses and toggles the output clock every 3 input clock cycles. The output clock frequency will be one-third of the input clock frequency, achieved by counting and resetting the counter at 3.

Syntax

This is the basic syntax pattern for a clock divider by 3 in VHDL:

• Entity: Defines the input clock and output divided clock signals.
• Architecture: Contains a process triggered by the rising edge of the input clock.
• Counter: A signal that counts from 0 to 2 (3 counts total).
• Output clock toggle: Changes state when the counter reaches 2, then resets.

vhdl

entity ClockDividerBy3 is
    Port (
        clk_in  : in  std_logic;
        reset   : in  std_logic;
        clk_out : out std_logic
    );
end ClockDividerBy3;

architecture Behavioral of ClockDividerBy3 is
    signal count : integer range 0 to 2 := 0;
    signal clk_div : std_logic := '0';
begin
    process(clk_in, reset)
    begin
        if reset = '1' then
            count <= 0;
            clk_div <= '0';
        elsif rising_edge(clk_in) then
            if count = 2 then
                count <= 0;
                clk_div <= not clk_div;
            else
                count <= count + 1;
            end if;
        end if;
    end process;

    clk_out <= clk_div;
end Behavioral;

Example

This example shows a complete VHDL module that divides an input clock by 3. The output clock toggles every 3 input clock cycles, effectively reducing the frequency to one-third.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ClockDividerBy3 is
    Port (
        clk_in  : in  std_logic;
        reset   : in  std_logic;
        clk_out : out std_logic
    );
end ClockDividerBy3;

architecture Behavioral of ClockDividerBy3 is
    signal count : integer range 0 to 2 := 0;
    signal clk_div : std_logic := '0';
begin
    process(clk_in, reset)
    begin
        if reset = '1' then
            count <= 0;
            clk_div <= '0';
        elsif rising_edge(clk_in) then
            if count = 2 then
                count <= 0;
                clk_div <= not clk_div;
            else
                count <= count + 1;
            end if;
        end if;
    end process;

    clk_out <= clk_div;
end Behavioral;

Output

The output clock signal 'clk_out' toggles every 3 input clock cycles, producing a clock frequency that is one-third of 'clk_in'.

Common Pitfalls

Common mistakes when creating a clock divider by 3 include:

• Not resetting the counter properly, which can cause the output clock to behave unpredictably.
• Using an incorrect counter range or forgetting to toggle the output clock at the right count.
• Not handling the reset signal asynchronously or synchronously, leading to startup glitches.

Always ensure the counter resets at 3 counts and the output clock toggles exactly at that point.

vhdl

process(clk_in, reset)
begin
    if reset = '1' then
        count <= 0;
        clk_div <= '0';
    elsif rising_edge(clk_in) then
        if count = 2 then  -- Corrected: count should go up to 2 for divide by 3
            count <= 0;
            clk_div <= not clk_div;
        else
            count <= count + 1;
        end if;
    end if;
end process;

Quick Reference

Tips for implementing a clock divider by 3 in VHDL:

• Use a counter that counts from 0 to 2 (three states).
• Toggle the output clock when the counter reaches 2.
• Reset the counter and output clock on a reset signal.
• Use rising_edge(clk_in) for synchronous counting.
• Initialize signals to avoid unknown states at startup.

Key Takeaways

Use a 2-bit counter counting from 0 to 2 to divide the clock by 3.

Toggle the output clock signal when the counter reaches 2 and then reset the counter.

Always include a reset signal to initialize the counter and output clock safely.

Use rising_edge(clk_in) for synchronous and glitch-free clock division.

Check counter ranges carefully to avoid off-by-one errors in clock division.