VHDL Code for CRC Generator: Syntax and Example

A CRC generator in VHDL is typically implemented as a shift register with XOR feedback based on the CRC polynomial. The code uses a process triggered by clock and reset signals to update the CRC value for each input bit. This creates a hardware-friendly way to calculate CRC checksums.

Syntax

The CRC generator in VHDL uses a process block sensitive to the clock and reset signals. Inside, a shift register stores the current CRC value. XOR gates implement the polynomial feedback. The main parts are:

• clk: Clock signal to synchronize updates.
• reset: Resets the CRC register to zero.
• data_in: Input bit to be processed.
• crc_reg: Register holding the current CRC value.
• polynomial: Defines which bits to XOR for feedback.

vhdl

process(clk, reset)
begin
  if reset = '1' then
    crc_reg <= (others => '0');
  elsif rising_edge(clk) then
    crc_reg <= (crc_reg(2 downto 0) & '0') xor (feedback bit);
  end if;
end process;

Example

This example shows a 4-bit CRC generator using the polynomial x^4 + x + 1 (binary 10011). It processes one input bit per clock cycle and outputs the CRC value.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity crc4_generator is
  port(
    clk     : in std_logic;
    reset   : in std_logic;
    data_in : in std_logic;
    crc_out : out std_logic_vector(3 downto 0)
  );
end entity;

architecture behavioral of crc4_generator is
  signal crc_reg : std_logic_vector(3 downto 0) := (others => '0');
begin
  process(clk, reset)
    variable feedback : std_logic;
  begin
    if reset = '1' then
      crc_reg <= (others => '0');
    elsif rising_edge(clk) then
      feedback := data_in xor crc_reg(3);
      crc_reg(3) <= crc_reg(2);
      crc_reg(2) <= crc_reg(1);
      crc_reg(1) <= crc_reg(0) xor feedback;
      crc_reg(0) <= feedback;
    end if;
  end process;

  crc_out <= crc_reg;
end behavioral;

Output

When simulated, the crc_out signal updates each clock cycle with the CRC value for the input bits processed so far.

Common Pitfalls

Common mistakes when writing a CRC generator in VHDL include:

• Not resetting the CRC register properly, causing incorrect initial values.
• Incorrect polynomial implementation, leading to wrong CRC results.
• Mixing bit order or shifting direction, which changes the CRC calculation.
• Forgetting to synchronize input data with the clock.

Always verify the polynomial and test with known input-output pairs.

vhdl

wrong: crc_reg <= crc_reg(2 downto 0) & feedback; -- shifts right instead of left
right: crc_reg(3) <= crc_reg(2); -- shift left as in example

Quick Reference

Tips for writing a CRC generator in VHDL:

• Use a shift register sized to the CRC width.
• Implement XOR feedback according to the polynomial.
• Reset the register on reset signal.
• Process input bits synchronized to clock edges.
• Test with known CRC vectors for correctness.

Key Takeaways

Implement CRC as a shift register with XOR feedback based on the polynomial.

Always reset the CRC register to zero to start fresh calculations.

Synchronize input data and CRC updates with the clock signal.

Verify polynomial correctness and test with known input-output pairs.

Avoid shifting in the wrong direction or incorrect feedback logic.