VHDL Code for Frequency Divider: Syntax and Example

A frequency divider in VHDL uses a counter to reduce the input clock frequency by toggling an output signal after counting a set number of input clock cycles. The basic code includes a process triggered by the clock edge that increments a counter and toggles the output when the count reaches half the division factor, using if and process statements.

Syntax

The basic syntax for a frequency divider in VHDL involves a process block sensitive to the clock signal. Inside, a counter variable increments on each clock rising edge. When the counter reaches a preset value, the output clock signal toggles and the counter resets.

• process(clk): Runs on clock edge.
• if rising_edge(clk): Detects clock rising edge.
• counter: Counts clock cycles.
• output_signal <= not output_signal: Toggles output.

vhdl

process(clk)
begin
  if rising_edge(clk) then
    if counter = DIVIDE_BY/2 - 1 then
      output_signal <= not output_signal;
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

Example

This example shows a frequency divider that halves the input clock frequency. The output clock toggles every two input clock cycles, effectively dividing the frequency by 2.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity freq_divider is
  Port (
    clk_in  : in  STD_LOGIC;
    reset_n : in  STD_LOGIC;
    clk_out : out STD_LOGIC
  );
end freq_divider;

architecture Behavioral of freq_divider is
  signal counter : unsigned(0 downto 0) := (others => '0');
  signal clk_div : STD_LOGIC := '0';
  constant DIVIDE_BY : integer := 2;
begin
  process(clk_in, reset_n)
  begin
    if reset_n = '0' then
      counter <= (others => '0');
      clk_div <= '0';
    elsif rising_edge(clk_in) then
      if counter = DIVIDE_BY/2 - 1 then
        clk_div <= not clk_div;
        counter <= (others => '0');
      else
        counter <= counter + 1;
      end if;
    end if;
  end process;

  clk_out <= clk_div;
end Behavioral;

Output

The output signal clk_out toggles every 2 input clock cycles, producing a clock frequency half of clk_in.

Common Pitfalls

Common mistakes when writing a frequency divider in VHDL include:

• Not resetting the counter properly, causing incorrect frequency output.
• Using an incorrect counter size that cannot hold the required count.
• Forgetting to toggle the output signal, resulting in no frequency division.
• Using asynchronous reset incorrectly, which can cause glitches.

Always ensure the counter width matches the division factor and the output toggles exactly at half the count.

vhdl

process(clk_in, reset_n)
begin
  if reset_n = '0' then
    counter <= (others => '0');
    clk_div <= '0';
  elsif rising_edge(clk_in) then
    if counter = DIVIDE_BY - 1 then  -- Incorrect: toggling at full count
      clk_div <= not clk_div;
      counter <= (others => '0');
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

-- Correct toggling at half count:
process(clk_in, reset_n)
begin
  if reset_n = '0' then
    counter <= (others => '0');
    clk_div <= '0';
  elsif rising_edge(clk_in) then
    if counter = DIVIDE_BY/2 - 1 then
      clk_div <= not clk_div;
      counter <= (others => '0');
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

Quick Reference

• Use a counter to track clock cycles.
• Toggle output at half the division count.
• Reset counter and output on reset signal.
• Choose counter width to fit division factor.
• Use rising_edge(clk) for synchronous operation.

Key Takeaways

A frequency divider toggles output after counting half the division factor clock cycles.

Always reset the counter and output signal to avoid glitches.

Use a counter wide enough to hold the maximum count value.

Toggle output on the rising edge of the input clock for synchronous design.

Test your design with different division factors to ensure correctness.