VHDL Code for JK Flip Flop: Syntax and Example

A JK flip flop in VHDL can be coded using a process block sensitive to clock and asynchronous reset signals. The J and K inputs control the flip flop behavior, toggling or setting/resetting the output Q on the rising edge of the clock.

Syntax

The JK flip flop in VHDL is typically written inside a process block sensitive to the clock and reset signals. Inside, you check for the reset condition first, then on the rising edge of the clock, update the output Q based on the J and K inputs.

• clk: Clock input triggering state changes on rising edge.
• reset: Asynchronous reset to initialize output.
• J, K: Control inputs determining flip flop behavior.
• Q: Output storing the flip flop state.

vhdl

process(clk, reset) is
begin
  if reset = '1' then
    Q <= '0';  -- Reset output to 0
  elsif rising_edge(clk) then
    if J = '0' and K = '0' then
      Q <= Q;  -- No change
    elsif J = '0' and K = '1' then
      Q <= '0';  -- Reset
    elsif J = '1' and K = '0' then
      Q <= '1';  -- Set
    else
      Q <= not Q;  -- Toggle
    end if;
  end if;
end process;

Example

This example shows a complete JK flip flop entity and architecture. It uses an asynchronous reset and updates output Q on the rising edge of clk based on inputs J and K.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity JK_FF is
  Port (
    clk   : in  STD_LOGIC;
    reset : in  STD_LOGIC;
    J     : in  STD_LOGIC;
    K     : in  STD_LOGIC;
    Q     : out STD_LOGIC
  );
end JK_FF;

architecture Behavioral of JK_FF is
  signal Q_int : STD_LOGIC := '0';
begin
  process(clk, reset)
  begin
    if reset = '1' then
      Q_int <= '0';
    elsif rising_edge(clk) then
      if J = '0' and K = '0' then
        Q_int <= Q_int;  -- No change
      elsif J = '0' and K = '1' then
        Q_int <= '0';  -- Reset
      elsif J = '1' and K = '0' then
        Q_int <= '1';  -- Set
      else
        Q_int <= not Q_int;  -- Toggle
      end if;
    end if;
  end process;

  Q <= Q_int;
end Behavioral;

Output

No direct console output; Q changes according to J, K, clk, and reset signals during simulation.

Common Pitfalls

Common mistakes when coding JK flip flops in VHDL include:

• Not including the asynchronous reset in the sensitivity list, causing simulation mismatches.
• Forgetting to check for the rising edge of the clock properly.
• Not handling the J=K=0 case correctly, which should keep the output unchanged.
• Assigning output Q directly inside the process without using a signal for intermediate storage.

vhdl

process(clk) is  -- Missing reset in sensitivity list (wrong)
begin
  if reset = '1' then  -- This won't work properly
    Q <= '0';
  elsif rising_edge(clk) then
    -- rest of code
  end if;
end process;

-- Correct way:
process(clk, reset) is
begin
  if reset = '1' then
    Q <= '0';
  elsif rising_edge(clk) then
    -- rest of code
  end if;
end process;

Quick Reference

Input J	Input K	Next State Q(t+1)
0	0	Q(t) (No change)
0	1	0 (Reset)
1	0	1 (Set)
1	1	Toggle Q(t)

Key Takeaways

Use a process sensitive to clock and asynchronous reset for JK flip flop in VHDL.

Check reset first, then update output on rising clock edge based on J and K inputs.

Handle the J=K=0 case to keep output unchanged and J=K=1 to toggle output.

Include reset in the sensitivity list to avoid simulation issues.

Use an internal signal for output state before assigning to output port.