Signal vs Variable in VHDL: Key Differences and Usage

In VHDL, a signal represents a wire or connection that updates its value after a process completes, while a variable holds temporary data that updates immediately within a process. Signals are used for communication between processes, and variables are used for local calculations inside a process.

Quick Comparison

Here is a quick table showing the main differences between signal and variable in VHDL.

Aspect	Signal	Variable
Scope	Visible outside the process	Local to the process
Update timing	Updates after process execution (delta cycle)	Updates immediately
Usage	For communication between processes	For temporary calculations inside a process
Initial value	Can have default initial value	Can have default initial value
Memory type	Represents hardware wire/register	Represents temporary storage
Assignment operator	<=	:=

Key Differences

Signals in VHDL model physical connections like wires or registers. When you assign a value to a signal inside a process, the new value does not take effect immediately. Instead, it schedules an update that happens after the process finishes, during the simulation's delta cycle. This means if you read the signal again inside the same process execution, you still see the old value.

Variables, on the other hand, are local to the process or subprogram where they are declared. When you assign a value to a variable, it updates immediately, so any following statements in the same process see the new value. Variables are useful for intermediate calculations or temporary storage within a process.

Because signals represent hardware connections, they are visible and can be read or driven by multiple processes. Variables are purely local and cannot be accessed outside their process. Also, signals use the assignment operator <=, while variables use :=.

Signal Code Example

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SignalExample is
    Port ( clk : in STD_LOGIC;
           a   : in STD_LOGIC;
           b   : out STD_LOGIC);
end SignalExample;

architecture Behavioral of SignalExample is
    signal temp_signal : STD_LOGIC := '0';
begin
    process(clk)
    begin
        if rising_edge(clk) then
            temp_signal <= a;  -- signal assignment
            b <= temp_signal;  -- reads old value of temp_signal
        end if;
    end process;
end Behavioral;

Output

Output b updates one clock cycle after input a changes because temp_signal updates after the process.

Variable Equivalent

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity VariableExample is
    Port ( clk : in STD_LOGIC;
           a   : in STD_LOGIC;
           b   : out STD_LOGIC);
end VariableExample;

architecture Behavioral of VariableExample is
begin
    process(clk)
        variable temp_var : STD_LOGIC := '0';
    begin
        if rising_edge(clk) then
            temp_var := a;  -- variable assignment
            b <= temp_var; -- reads updated value immediately
        end if;
    end process;
end Behavioral;

Output

Output b updates immediately with input a on the same clock cycle.

When to Use Which

Choose signal when you need to model hardware connections or communicate values between processes, as signals reflect real hardware wires and registers with delayed updates. Use variable inside a process for temporary calculations or when you want immediate updates within the same process execution. Variables are best for intermediate steps that do not need to be visible outside the process.

In summary, use signals for inter-process communication and variables for local, immediate data handling.

Key Takeaways

Signals update their value after the process finishes, reflecting hardware behavior.

Variables update immediately within a process and are local to that process.

Use signals for communication between processes and variables for local calculations.

Signal assignments use '<= ', variables use ':='.

Choosing correctly improves simulation accuracy and hardware design clarity.