How to Do Shift Operation in VHDL: Syntax and Examples

In VHDL, shift operations can be done using the shift_left and shift_right functions or the operators sll (shift left logical) and srl (shift right logical). These operations move bits left or right within a vector, filling with zeros on the opposite side.

Syntax

VHDL provides two main ways to perform shift operations on bit vectors or std_logic_vectors:

• Functions: shift_left(data, amount) and shift_right(data, amount) from the numeric_std package.
• Operators: sll (shift left logical) and srl (shift right logical) used as data sll amount or data srl amount.

Both shift left and shift right move bits by the specified amount, inserting zeros on the opposite side.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Using functions
shifted_left  <= std_logic_vector(shift_left(unsigned(data), 2));
shifted_right <= std_logic_vector(shift_right(unsigned(data), 3));

-- Using operators
shifted_left_op  <= data sll 2;
shifted_right_op <= data srl 3;

Example

This example shows how to shift a 8-bit std_logic_vector left and right by 2 bits using both functions and operators.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity shift_example is
    port(
        data_in  : in  std_logic_vector(7 downto 0);
        shifted_left_func  : out std_logic_vector(7 downto 0);
        shifted_right_func : out std_logic_vector(7 downto 0);
        shifted_left_op    : out std_logic_vector(7 downto 0);
        shifted_right_op   : out std_logic_vector(7 downto 0)
    );
end shift_example;

architecture behavior of shift_example is
begin
    shifted_left_func  <= std_logic_vector(shift_left(unsigned(data_in), 2));
    shifted_right_func <= std_logic_vector(shift_right(unsigned(data_in), 2));

    shifted_left_op  <= data_in sll 2;
    shifted_right_op <= data_in srl 2;
end behavior;

Common Pitfalls

• Type mismatch: Shift functions require unsigned or signed types, so you must convert std_logic_vector before shifting.
• Using wrong operators: sll and srl only work on std_logic_vector or bit_vector, not on integers.
• Confusing shift with rotate: Shift inserts zeros, while rotate moves bits around circularly.

Wrong example:

shifted <= shift_left(data_in, 2); -- if data_in is std_logic_vector without conversion

Right example:

shifted <= std_logic_vector(shift_left(unsigned(data_in), 2));

Quick Reference

Operation	Syntax	Description
Shift Left (function)	shift_left(unsigned_vector, amount)	Shifts bits left, inserts zeros on right
Shift Right (function)	shift_right(unsigned_vector, amount)	Shifts bits right, inserts zeros on left
Shift Left Logical (operator)	vector sll amount	Shifts bits left logically, zeros on right
Shift Right Logical (operator)	vector srl amount	Shifts bits right logically, zeros on left

Key Takeaways

Use shift_left and shift_right functions with unsigned or signed types, converting std_logic_vector as needed.

Use sll and srl operators directly on std_logic_vector or bit_vector for simple logical shifts.

Shift operations move bits and fill with zeros; they do not rotate bits around.

Always check data types to avoid errors when shifting in VHDL.

Shift functions come from ieee.numeric_std package, so include it in your code.