What is Sensitivity List in VHDL: Explanation and Example

In VHDL, a sensitivity list is a list of signals that trigger a process to run whenever any of them change. It tells the simulator which signals to watch so the process executes only when needed, making designs efficient and reactive.

How It Works

Think of a sensitivity list like a watchlist for a process. Imagine you have a room with several light switches, but you only want to react when certain switches (signals) are flipped. The sensitivity list tells the process exactly which switches (signals) to watch.

When any signal in this list changes, the process wakes up and runs its code. If none of these signals change, the process stays idle, saving time and resources. This is like only checking your mailbox when you expect mail, instead of every minute.

Without a sensitivity list, the process wouldn't know when to run automatically, which can cause incorrect or inefficient behavior in your digital design.

Example

This example shows a simple VHDL process with a sensitivity list containing signals a and b. The process adds these signals and updates sum whenever a or b changes.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity SensitivityExample is
    Port ( a : in STD_LOGIC_VECTOR(3 downto 0);
           b : in STD_LOGIC_VECTOR(3 downto 0);
           sum : out STD_LOGIC_VECTOR(4 downto 0));
end SensitivityExample;

architecture Behavioral of SensitivityExample is
begin
    process(a, b)  -- sensitivity list
    begin
        sum <= std_logic_vector(unsigned(a) + unsigned(b));
    end process;
end Behavioral;

When to Use

Use a sensitivity list in VHDL whenever you write a process block that should react to changes in signals. It is essential for combinational logic where outputs depend immediately on inputs.

For example, in digital circuits like adders, multiplexers, or simple logic gates, sensitivity lists ensure the process updates outputs only when inputs change. This avoids unnecessary computations and keeps simulation accurate.

In clocked (sequential) processes, the sensitivity list usually contains only the clock and reset signals, because the process should run only on clock edges or resets.

Key Points

• The sensitivity list controls when a process runs by listing signals to watch.
• It is required for combinational processes to update outputs correctly.
• In clocked processes, the sensitivity list typically includes clock and reset signals only.
• Leaving out signals from the sensitivity list can cause simulation mismatches and incorrect behavior.

Key Takeaways

A sensitivity list tells a VHDL process which signals to watch for changes.

Processes run only when signals in their sensitivity list change, improving efficiency.

Always include all input signals in the sensitivity list for combinational logic.

For clocked processes, include only clock and reset signals in the sensitivity list.

Missing signals in the sensitivity list can cause simulation errors and wrong outputs.