How to Simulate VHDL Using GHDL: Step-by-Step Guide

To simulate VHDL using ghdl, first analyze your VHDL files with ghdl -a, then elaborate the design with ghdl -e, and finally run the simulation using ghdl -r. This sequence compiles, prepares, and executes your VHDL testbench to show simulation results.

Syntax

GHDL simulation involves three main commands:

• Analyze: ghdl -a <file.vhdl> compiles the VHDL source.
• Elaborate: ghdl -e <entity_name> prepares the design for simulation.
• Run: ghdl -r <entity_name> executes the simulation and shows output.

Replace <file.vhdl> with your VHDL file and <entity_name> with your top-level design or testbench entity.

bash

ghdl -a my_design.vhdl
ghdl -e my_testbench
ghdl -r my_testbench

Example

This example shows a simple VHDL testbench for a NOT gate and how to simulate it with GHDL.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity not_gate is
    port(
        a : in std_logic;
        y : out std_logic
    );
end entity not_gate;

architecture behavior of not_gate is
begin
    y <= not a;
end architecture behavior;

entity tb_not_gate is
end entity tb_not_gate;

architecture testbench of tb_not_gate is
    signal a, y : std_logic := '0';
begin
    uut: entity work.not_gate
        port map(a => a, y => y);

    process
    begin
        a <= '0';
        wait for 10 ns;
        a <= '1';
        wait for 10 ns;
        wait;
    end process;
end architecture testbench;

Running the Example

Use these commands to simulate the example above:

bash

ghdl -a not_gate.vhdl
ghdl -a tb_not_gate.vhdl
ghdl -e tb_not_gate
ghdl -r tb_not_gate --vcd=output.vcd

Output

GHDL simulation for tb_not_gate
Time: 0 ns, a=0, y=1
Time: 10 ns, a=1, y=0
Simulation finished.

Common Pitfalls

• Forgetting to analyze all VHDL files before elaboration causes errors.
• Using the wrong entity name in ghdl -e or ghdl -r leads to "entity not found" errors.
• Not specifying a testbench entity for elaboration and run will fail simulation.
• Ignoring simulation output or waveform generation flags like --vcd=output.vcd can limit debugging.

bash

ghdl -a design.vhdl
# Missing testbench analysis
ghdl -e design
# Error: entity not found

# Correct way:
ghdl -a testbench.vhdl
ghdl -e testbench
ghdl -r testbench

Quick Reference

Command	Purpose	Example
ghdl -a	Analyze (compile) VHDL source	ghdl -a my_design.vhdl
ghdl -e	Elaborate design or testbench	ghdl -e tb_not_gate
ghdl -r	Run simulation	ghdl -r tb_not_gate --vcd=wave.vcd

Key Takeaways

Always analyze all VHDL files before elaboration and running simulation.

Use the testbench entity name with ghdl -e and ghdl -r commands.

Add --vcd=filename.vcd to generate waveform files for visual debugging.

Check for typos in entity names to avoid "entity not found" errors.

Run simulation commands in order: analyze, elaborate, then run.