VHDL Code for Arbiter: Syntax, Example, and Tips

An arbiter in VHDL controls access to a shared resource by multiple requesters. You write it using a process that checks requests and grants access fairly, often using a priority or round-robin scheme. The arbiter outputs grant signals based on input requests.

Syntax

An arbiter in VHDL typically uses input signals for requests and outputs grant signals. It uses a process block sensitive to requests and clock signals. Inside, it checks requests and assigns grants based on priority or fairness.

Key parts:

• entity: Defines inputs (requests) and outputs (grants).
• architecture: Contains the logic to decide which request to grant.
• process: Runs on clock or request changes to update grants.

vhdl

entity Arbiter is
    Port (
        clk     : in  std_logic;
        reset   : in  std_logic;
        req     : in  std_logic_vector(3 downto 0); -- 4 request lines
        grant   : out std_logic_vector(3 downto 0)  -- 4 grant lines
    );
end Arbiter;

architecture Behavioral of Arbiter is
begin
    process(clk, reset)
    begin
        if reset = '1' then
            grant <= (others => '0');
        elsif rising_edge(clk) then
            -- Grant logic here
        end if;
    end process;
end Behavioral;

Example

This example shows a simple priority arbiter for 4 request lines. It grants access to the highest priority request (lowest index) that is active.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Arbiter is
    Port (
        clk     : in  std_logic;
        reset   : in  std_logic;
        req     : in  std_logic_vector(3 downto 0);
        grant   : out std_logic_vector(3 downto 0)
    );
end Arbiter;

architecture Behavioral of Arbiter is
begin
    process(clk, reset)
    begin
        if reset = '1' then
            grant <= (others => '0');
        elsif rising_edge(clk) then
            if req(0) = '1' then
                grant <= "0001";
            elsif req(1) = '1' then
                grant <= "0010";
            elsif req(2) = '1' then
                grant <= "0100";
            elsif req(3) = '1' then
                grant <= "1000";
            else
                grant <= (others => '0');
            end if;
        end if;
    end process;
end Behavioral;

Output

When run with requests, the arbiter grants the first active request in priority order: req(0) highest, req(3) lowest.

Common Pitfalls

Common mistakes when writing an arbiter in VHDL include:

• Not resetting the grant signals properly, causing undefined outputs.
• Granting multiple requests at once when only one should be granted.
• Ignoring clock edges or asynchronous resets, leading to unstable behavior.
• Not handling the case when no requests are active.

Always use a clocked process and clear grants on reset.

vhdl

Wrong approach (multiple grants possible):
process(clk)
begin
    if rising_edge(clk) then
        grant <= req; -- directly passing requests as grants
    end if;
end process;

Right approach (single grant):
process(clk, reset)
begin
    if reset = '1' then
        grant <= (others => '0');
    elsif rising_edge(clk) then
        if req(0) = '1' then
            grant <= "0001";
        elsif req(1) = '1' then
            grant <= "0010";
        else
            grant <= (others => '0');
        end if;
    end if;
end process;

Quick Reference

Tips for writing a VHDL arbiter:

• Use a clocked process with reset for stable operation.
• Grant only one request at a time to avoid conflicts.
• Implement priority or round-robin logic depending on fairness needs.
• Clear grants when no requests are active.
• Test with different request patterns to verify behavior.

Key Takeaways

Use a clocked process with reset to control grant signals safely.

Grant only one request at a time based on priority or fairness.

Always clear grants when no requests are active to avoid conflicts.

Test arbiter logic with various request inputs to ensure correct behavior.

Avoid directly passing requests as grants without arbitration logic.