Signal vs Variable Assignment Inside Process in VHDL: Key Differences

In VHDL, signal assignments inside a process update after the process completes, while variable assignments update immediately within the process. This means signals reflect changes in the next simulation cycle, but variables reflect changes instantly during process execution.

Quick Comparison

Here is a quick table comparing signal and variable assignments inside a VHDL process.

Factor	Signal Assignment	Variable Assignment
Update Timing	After process ends (delta cycle)	Immediately during process execution
Scope	Visible outside the process	Local to the process
Usage	Model hardware wires/registers	Temporary storage/calculations
Multiple Assignments	Last assignment in process takes effect	Each assignment updates value instantly
Simulation Effect	Changes seen in next simulation cycle	Changes seen immediately within process

Key Differences

Signal assignments inside a process do not update the signal value immediately. Instead, they schedule the update to happen after the process finishes, during the simulation's delta cycle. This means if you assign a signal multiple times in one process run, only the last assignment is effective.

On the other hand, variable assignments update the variable's value instantly within the process. This allows you to use the updated variable value immediately in subsequent statements inside the same process execution.

Signals represent hardware connections and their delayed update models real hardware behavior, while variables are like temporary memory used for calculations or intermediate results inside the process.

Code Comparison

This example shows how signal assignment delays the update, but variable assignment updates immediately inside a process.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity signal_vs_variable is
    port(
        clk : in std_logic;
        out_sig : out std_logic;
        out_var : out std_logic
    );
end entity;

architecture behavior of signal_vs_variable is
    signal sig : std_logic := '0';
begin
    process(clk)
        variable var : std_logic := '0';
    begin
        if rising_edge(clk) then
            sig <= '1';  -- signal assigned
            var := '1';  -- variable assigned
            out_sig <= sig;  -- outputs current signal value
            out_var <= var;  -- outputs current variable value
        end if;
    end process;
end behavior;

Output

On rising edge, out_sig outputs previous sig value (0), out_var outputs updated var value (1)

Variable Equivalent

This code shows how variable assignment updates immediately and can be used for intermediate calculations inside a process.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity variable_example is
    port(
        clk : in std_logic;
        out_var : out std_logic
    );
end entity;

architecture behavior of variable_example is
begin
    process(clk)
        variable temp_var : std_logic := '0';
    begin
        if rising_edge(clk) then
            temp_var := '1';  -- immediate update
            if temp_var = '1' then
                out_var <= '1';  -- uses updated variable value
            else
                out_var <= '0';
            end if;
        end if;
    end process;
end behavior;

Output

On rising edge, out_var outputs '1' immediately using updated variable

When to Use Which

Choose signal when modeling hardware elements that need to reflect changes outside the process or across clock cycles, like flip-flops or wires. Signals are essential for communication between processes and for outputs.

Choose variable inside a process when you need immediate updates for calculations, temporary storage, or to avoid multiple signal assignments that cause simulation delays. Variables help write cleaner, more efficient sequential logic inside processes.

Key Takeaways

Signal assignments update after the process finishes, reflecting changes in the next simulation cycle.

Variable assignments update immediately within the process and can be used for intermediate calculations.

Use signals to model hardware connections and communication between processes.

Use variables for temporary storage and immediate value updates inside a process.

Multiple signal assignments in one process only keep the last value, but variables update on each assignment.