VHDL Code for Pulse Generator: Syntax and Example

A pulse generator in VHDL creates a signal that goes high for a fixed time and then low. You can write it using a process with a clock and counters to control pulse width and period. The pulse output toggles high for the desired duration, then returns low.

Syntax

A pulse generator in VHDL typically uses a process block triggered by a clock signal. Inside, counters track time to set the pulse width and period. The output signal is set high during the pulse duration and low otherwise.

Key parts:

• clk: Clock input to synchronize timing.
• pulse_out: Output signal that generates the pulse.
• counter: Counts clock cycles to control pulse timing.
• pulse_width and period: Constants defining pulse duration and repetition.

vhdl

process(clk)
begin
  if rising_edge(clk) then
    if counter < period then
      counter <= counter + 1;
    else
      counter <= 0;
    end if;

    if counter < pulse_width then
      pulse_out <= '1';
    else
      pulse_out <= '0';
    end if;
  end if;
end process;

Example

This example shows a pulse generator that creates a pulse of 10 clock cycles high every 50 clock cycles. The pulse_out signal goes high for 10 cycles and low for 40 cycles repeatedly.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity pulse_generator is
  Port (
    clk       : in  STD_LOGIC;
    pulse_out : out STD_LOGIC
  );
end pulse_generator;

architecture Behavioral of pulse_generator is
  constant pulse_width : integer := 10;
  constant period      : integer := 50;
  signal counter      : integer range 0 to period := 0;
begin
  process(clk)
  begin
    if rising_edge(clk) then
      if counter < period then
        counter <= counter + 1;
      else
        counter <= 0;
      end if;

      if counter < pulse_width then
        pulse_out <= '1';
      else
        pulse_out <= '0';
      end if;
    end if;
  end process;
end Behavioral;

Output

pulse_out signal is '1' for 10 clock cycles, then '0' for 40 clock cycles, repeating continuously.

Common Pitfalls

Common mistakes when writing a pulse generator in VHDL include:

• Not resetting the counter properly, causing the pulse timing to drift.
• Using incorrect comparison operators, e.g., <= instead of <, which can change pulse length.
• Forgetting to use rising_edge(clk) for synchronous logic, leading to glitches.
• Not defining the counter range to match the period, causing overflow errors.

vhdl

process(clk)
begin
  if clk = '1' then  -- Wrong: should use rising_edge(clk)
    if counter < period then  -- Wrong: should be < period
      counter <= counter + 1;
    else
      counter <= 0;
    end if;

    if counter < pulse_width then  -- Wrong: should be < pulse_width
      pulse_out <= '1';
    else
      pulse_out <= '0';
    end if;
  end if;
end process;

Quick Reference

• Use rising_edge(clk) for clock detection.
• Define constants for pulse_width and period to easily adjust timing.
• Keep counter range within 0 to period to avoid overflow.
• Set output high when counter < pulse_width, else low.

Key Takeaways

Use a synchronous process with rising_edge(clk) to create stable pulses.

Control pulse width and period with counters and constants for easy timing adjustment.

Reset counters properly to maintain consistent pulse timing.

Compare counters with less-than operators to get correct pulse durations.

Define signal ranges to prevent overflow and simulation errors.